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SPI NOR core changes:

Browse source 
- move vendor specific code out of the core into vendor drivers.
 - unify all function and object names in the vendor modules.
 - make setup() callback optional to improve readability.
 - skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
   declaration.
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAmInffUACgkQS1VPR6WN
 FOn9fwf/SCIvgoScBNeQjW4cGTmh11oO+O8i2umibq0pQDLrNF6Ul7ykY6Fdm4Dc
 +Ce7c4Vp0O+DRphIkaK5MtNgRmXMOQbqUKcNAQftFS0wCtJ+QVQzOvkVGS3jQA74
 KVEY3Jiup3Q5qknBg0r890ENwRLmcGJaPi5DAO+uHcf6ItTpwjv3z6C2ZUeiH6UK
 PMSwZgd86dwwH2eU4G5EoAjA+nqOcVvH0V1F49DFsGZ3kkmUS6nMNnSpb5SykszT
 4uq+7+c3E2UOC0TlUkyX/xTv4DoZZDi6qqVEaV14bELL1a0FdltjKyIuWTds1Tei
 rwPhEOkqOpSnBVjlUWb7icwef21NWg==
 =QFe+
 -----END PGP SIGNATURE-----

Merge tag 'spi-nor/for-5.18' into mtd/next

SPI NOR core changes:
- move vendor specific code out of the core into vendor drivers.
- unify all function and object names in the vendor modules.
- make setup() callback optional to improve readability.
- skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
  declaration.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Miquel Raynal 2022-03-18 20:14:12 +01:00
commit 4e371d9965
1231 changed files with 13924 additions and 7456 deletions
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18
include/linux/mtd/spi-nor.h
View file

@ -47,8 +47,6 @@
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
@ -86,22 +84,12 @@
#define SPINOR_OP_BP 0x02 /* Byte program */
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
/* Used for S3AN flashes only */
#define SPINOR_OP_XSE 0x50 /* Sector erase */
#define SPINOR_OP_XPP 0x82 /* Page program */
#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
#define XSR_RDY BIT(7) /* Ready */
/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
@ -135,12 +123,6 @@
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
/* Flag Status Register bits */
#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
#define FSR_E_ERR BIT(5) /* Erase operation status */
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */