From 37d158366530eb2852397911ee5f79b4eebfe299 Mon Sep 17 00:00:00 2001
From: Jami Kettunen <jami.kettunen@protonmail.com>
Date: Sun, 11 Sep 2022 15:56:44 +0300
Subject: [PATCH] [HACK] drm/msm: Always report CTL status as started for
 MSM8998

This register always appears to read 0 on <SDM845 generations so simply
ignore it to avoid refreshing at ~3 Hz as seen on OnePlus 5 with a
command-mode panel with the following spammed in dmesg every time the
screen refreshes:

  [drm:_dpu_encoder_phys_cmd_wait_for_ctl_start:660] [dpu error]enc31 intf1 ctl start interrupt wait failed
  [drm:dpu_kms_wait_for_commit_done:525] [dpu error]wait for commit done returned -22
  ...
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6676c8..fcfedda5d75c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -98,7 +98,7 @@ static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
 
 static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx)
 {
-	return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0));
+	return true;
 }
 
 static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)