kybaaz/linux-xiaomi-chiron
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mlx5-next-2020-12-02

Browse source 
Low level mlx5 updates required by both netdev and rdma trees:
 
   net/mlx5: Treat host PF vport as other (non eswitch manager) vport
   net/mlx5: Enable host PF HCA after eswitch is initialized
   net/mlx5: Rename peer_pf to host_pf
   net/mlx5: Make API mlx5_core_is_ecpf accept const pointer
   net/mlx5: Export steering related functions
   net/mlx5: Expose other function ifc bits
   net/mlx5: Expose IP-in-IP TX and RX capability bits
   net/mlx5: Update the hardware interface definition for vhca state
   net/mlx5: Update the list of the PCI supported devices
   net/mlx5: Avoid exposing driver internal command helpers
   net/mlx5: Add ts_cqe_to_dest_cqn related bits
   net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits
   net/mlx5: Check dr mask size against mlx5_match_param size
   net/mlx5: Add sampler destination type
   net/mlx5: Add sample offload hardware bits and structures
 
 Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl/IOZcACgkQSD+KveBX
 +j4J8wgAuxwflrYrbCWXV7LE08J7T7ZHRDE+jEbaZ0Zp9mOsYDDpcifpKwy2EVRf
 RKcpMYh/GzAljmEpeWIAlMxmlpXhKWXTDruWCx73r1jvdXf/RU24/zQHa6BjeiDo
 rMB8bgiW4a66+z4LcN/U6ahbVM5gScBNEt2sS1OIi9ZInngGVo9FgfhYMpERPNcH
 3+mcHulCnGBNbbLwoTllOcgbxexn+xoByukg5Z0ddBJp007DMjzBIWDpDS0y2HaT
 jGo1LYONgRc3zoGVmdeu9F+tSsWBIgsaiyGxKj1T/8sZUaNz2TKj9VOiYIj9BLff
 cp6GRc88k7HWA4tImSHQiLbK6cx+yA==
 =mjvI
 -----END PGP SIGNATURE-----

Merge tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Saeed Mahameed says:

====================
mlx5-next-2020-12-02

Low level mlx5 updates required by both netdev and rdma trees.

* tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Treat host PF vport as other (non eswitch manager) vport
  net/mlx5: Enable host PF HCA after eswitch is initialized
  net/mlx5: Rename peer_pf to host_pf
  net/mlx5: Make API mlx5_core_is_ecpf accept const pointer
  net/mlx5: Export steering related functions
  net/mlx5: Expose other function ifc bits
  net/mlx5: Expose IP-in-IP TX and RX capability bits
  net/mlx5: Update the hardware interface definition for vhca state
  net/mlx5: Update the list of the PCI supported devices
  net/mlx5: Avoid exposing driver internal command helpers
  net/mlx5: Add ts_cqe_to_dest_cqn related bits
  net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits
  net/mlx5: Check dr mask size against mlx5_match_param size
  net/mlx5: Add sampler destination type
  net/mlx5: Add sample offload hardware bits and structures
====================

Link: https://lore.kernel.org/r/20201203011010.213440-1-saeedm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2020-12-02 17:28:36 -08:00
commit 32e417024f
20 changed files with 250 additions and 104 deletions
Download patch file Download diff file Expand all files Collapse all files

8
include/linux/mlx5/device.h
View file

@ -346,6 +346,7 @@ enum mlx5_event {
MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
@ -717,6 +718,11 @@ struct mlx5_eqe_sync_fw_update {
u8 sync_rst_state;
};
struct mlx5_eqe_vhca_state {
__be16 ec_function;
__be16 function_id;
} __packed;
union ev_data {
__be32 raw[7];
struct mlx5_eqe_cmd cmd;
@ -736,6 +742,7 @@ union ev_data {
struct mlx5_eqe_temp_warning temp_warning;
struct mlx5_eqe_xrq_err xrq_err;
struct mlx5_eqe_sync_fw_update sync_fw_update;
struct mlx5_eqe_vhca_state vhca_state;
} __packed;
struct mlx5_eqe {
@ -1076,6 +1083,7 @@ enum {
MLX5_MATCH_INNER_HEADERS = 1 << 2,
MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
};
enum {

8
include/linux/mlx5/driver.h
View file

@ -547,7 +547,7 @@ struct mlx5_priv {
atomic_t reg_pages;
struct list_head free_list;
int vfs_pages;
int peer_pf_pages;
int host_pf_pages;
struct mlx5_core_health health;
@ -888,10 +888,6 @@ enum {
CMD_ALLOWED_OPCODE_ALL,
};
int mlx5_cmd_init(struct mlx5_core_dev *dev);
void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
enum mlx5_cmdif_state cmdif_state);
void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
@ -1137,7 +1133,7 @@ static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
return dev->coredev_type == MLX5_COREDEV_VF;
}
static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
{
return dev->caps.embedded_cpu;
}

6
include/linux/mlx5/fs.h
View file

@ -50,6 +50,7 @@ enum {
MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
MLX5_FLOW_TABLE_TERMINATION = BIT(2),
MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
MLX5_FLOW_TABLE_OTHER_VPORT = BIT(4),
};
#define LEFTOVERS_RULE_NUM 2
@ -132,6 +133,7 @@ struct mlx5_flow_destination {
struct mlx5_pkt_reformat *pkt_reformat;
u8 flags;
} vport;
u32 sampler_id;
};
};
@ -173,9 +175,7 @@ mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
struct mlx5_flow_table *
mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
int prio,
int num_flow_table_entries,
u32 level, u16 vport);
struct mlx5_flow_table_attr *ft_attr, u16 vport);
struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(
struct mlx5_flow_namespace *ns,
int prio, u32 level);

94
include/linux/mlx5/mlx5_ifc.h
View file

@ -299,6 +299,8 @@ enum {
MLX5_CMD_OP_CREATE_UMEM = 0xa08,
MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
MLX5_CMD_OP_SYNC_STEERING = 0xb00,
MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
MLX5_CMD_OP_MAX
};
@ -623,6 +625,26 @@ struct mlx5_ifc_fte_match_set_misc3_bits {
u8 reserved_at_140[0xc0];
};
struct mlx5_ifc_fte_match_set_misc4_bits {
u8 prog_sample_field_value_0[0x20];
u8 prog_sample_field_id_0[0x20];
u8 prog_sample_field_value_1[0x20];
u8 prog_sample_field_id_1[0x20];
u8 prog_sample_field_value_2[0x20];
u8 prog_sample_field_id_2[0x20];
u8 prog_sample_field_value_3[0x20];
u8 prog_sample_field_id_3[0x20];
u8 reserved_at_100[0x100];
};
struct mlx5_ifc_cmd_pas_bits {
u8 pa_h[0x20];
@ -891,7 +913,10 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 tunnel_stateless_ipv4_over_vxlan[0x1];
u8 tunnel_stateless_ip_over_ip[0x1];
u8 insert_trailer[0x1];
u8 reserved_at_2b[0x5];
u8 reserved_at_2b[0x1];
u8 tunnel_stateless_ip_over_ip_rx[0x1];
u8 tunnel_stateless_ip_over_ip_tx[0x1];
u8 reserved_at_2e[0x2];
u8 max_vxlan_udp_ports[0x8];
u8 reserved_at_38[0x6];
u8 max_geneve_opt_len[0x1];
@ -1224,7 +1249,16 @@ enum mlx5_fc_bulk_alloc_bitmask {
#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_0[0x30];
u8 reserved_at_0[0x1f];
u8 vhca_resource_manager[0x1];
u8 reserved_at_20[0x3];
u8 event_on_vhca_state_teardown_request[0x1];
u8 event_on_vhca_state_in_use[0x1];
u8 event_on_vhca_state_active[0x1];
u8 event_on_vhca_state_allocated[0x1];
u8 event_on_vhca_state_invalid[0x1];
u8 reserved_at_28[0x8];
u8 vhca_id[0x10];
u8 reserved_at_40[0x40];
@ -1241,7 +1275,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 ece_support[0x1];
u8 reserved_at_a4[0x7];
u8 log_max_srq[0x5];
u8 reserved_at_b0[0x10];
u8 reserved_at_b0[0x2];
u8 ts_cqe_to_dest_cqn[0x1];
u8 reserved_at_b3[0xd];
u8 max_sgl_for_optimized_performance[0x8];
u8 log_max_cq_sz[0x8];
@ -1512,7 +1548,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 disable_local_lb_uc[0x1];
u8 disable_local_lb_mc[0x1];
u8 log_min_hairpin_wq_data_sz[0x5];
u8 reserved_at_3e8[0x3];
u8 reserved_at_3e8[0x2];
u8 vhca_state[0x1];
u8 log_max_vlan_list[0x5];
u8 reserved_at_3f0[0x3];
u8 log_max_current_mc_list[0x5];
@ -1580,7 +1617,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 max_num_of_monitor_counters[0x10];
u8 num_ppcnt_monitor_counters[0x10];
u8 reserved_at_640[0x10];
u8 max_num_sf[0x10];
u8 num_q_monitor_counters[0x10];
u8 reserved_at_660[0x20];
@ -1616,6 +1653,7 @@ enum mlx5_flow_destination_type {
MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
@ -1668,7 +1706,9 @@ struct mlx5_ifc_fte_match_param_bits {
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
u8 reserved_at_a00[0x600];
struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
u8 reserved_at_c00[0x400];
};
enum {
@ -3289,8 +3329,12 @@ struct mlx5_ifc_sqc_bits {
u8 reserved_at_80[0x10];
u8 hairpin_peer_vhca[0x10];
u8 reserved_at_a0[0x50];
u8 reserved_at_a0[0x20];
u8 reserved_at_c0[0x8];
u8 ts_cqe_to_dest_cqn[0x18];
u8 reserved_at_e0[0x10];
u8 packet_pacing_rate_limit_index[0x10];
u8 tis_lst_sz[0x10];
u8 reserved_at_110[0x10];
@ -4204,7 +4248,11 @@ struct mlx5_ifc_set_hca_cap_in_bits {
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x40];
u8 other_function[0x1];
u8 reserved_at_41[0xf];
u8 function_id[0x10];
u8 reserved_at_60[0x20];
union mlx5_ifc_hca_cap_union_bits capability;
};
@ -5461,6 +5509,7 @@ enum {
MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
};
struct mlx5_ifc_query_flow_group_out_bits {
@ -10657,11 +10706,13 @@ struct mlx5_ifc_affiliated_event_header_bits {
enum {
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
};
enum {
MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
};
enum {
@ -10736,6 +10787,33 @@ struct mlx5_ifc_create_encryption_key_in_bits {
struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
};
struct mlx5_ifc_sampler_obj_bits {
u8 modify_field_select[0x40];
u8 table_type[0x8];
u8 level[0x8];
u8 reserved_at_50[0xf];
u8 ignore_flow_level[0x1];
u8 sample_ratio[0x20];
u8 reserved_at_80[0x8];
u8 sample_table_id[0x18];
u8 reserved_at_a0[0x8];
u8 default_table_id[0x18];
u8 sw_steering_icm_address_rx[0x40];
u8 sw_steering_icm_address_tx[0x40];
u8 reserved_at_140[0xa0];
};
struct mlx5_ifc_create_sampler_obj_in_bits {
struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
struct mlx5_ifc_sampler_obj_bits sampler_object;
};
enum {
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,