media: camss: Add support for CSIPHY hardware version Titan 170
Add register definitions for version 170 of the Titan architecture and implement support for the CSIPHY subdevice. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Robert Foss
Mauro Carvalho Chehab
parent
eebe6d00e9
commit
2f8b67195e
3 changed files with 288 additions and 31 deletions
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@ -47,6 +47,105 @@
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
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#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n))
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#define CSIPHY_DEFAULT_PARAMS 0
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#define CSIPHY_LANE_ENABLE 1
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#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2
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#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3
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#define CSIPHY_DNP_PARAMS 4
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#define CSIPHY_2PH_REGS 5
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#define CSIPHY_3PH_REGS 6
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struct csiphy_reg_t {
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s32 reg_addr;
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s32 reg_data;
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s32 delay;
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u32 csiphy_param_type;
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};
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static const struct
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csiphy_reg_t lane_regs_sdm845[5][14] = {
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{
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{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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};
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static void csiphy_hw_version_read(struct csiphy_device *csiphy,
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struct device *dev)
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{
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@ -134,25 +233,13 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
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return settle_cnt;
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}
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static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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s64 link_freq, u8 lane_mask)
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static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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u8 settle_cnt)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val, l = 0;
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int i;
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settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
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val = BIT(c->clk.pos);
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for (i = 0; i < c->num_data; i++)
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val |= BIT(c->data[i].pos * 2);
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
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val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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int i, l = 0;
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u8 val;
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for (i = 0; i <= c->num_data; i++) {
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if (i == c->num_data)
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@ -206,6 +293,64 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
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}
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static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
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u8 settle_cnt)
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{
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int i, l;
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u32 val;
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for (l = 0; l < 5; l++) {
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for (i = 0; i < 14; i++) {
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const struct csiphy_reg_t *r = &lane_regs_sdm845[l][i];
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switch (r->csiphy_param_type) {
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case CSIPHY_SETTLE_CNT_LOWER_BYTE:
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val = settle_cnt & 0xff;
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break;
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case CSIPHY_DNP_PARAMS:
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continue;
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default:
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val = r->reg_data;
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break;
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}
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writel_relaxed(val, csiphy->base + r->reg_addr);
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}
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}
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}
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static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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s64 link_freq, u8 lane_mask)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val;
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int i;
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settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
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val = BIT(c->clk.pos);
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for (i = 0; i < c->num_data; i++)
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val |= BIT(c->data[i].pos * 2);
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
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val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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val = 0x02;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(7));
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val = 0x00;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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if (csiphy->camss->version == CAMSS_8x16 ||
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csiphy->camss->version == CAMSS_8x96)
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csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
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else if (csiphy->camss->version == CAMSS_845)
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csiphy_gen2_config_lanes(csiphy, settle_cnt);
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11));
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@ -73,6 +73,30 @@ static const struct csiphy_format csiphy_formats_8x96[] = {
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{ MEDIA_BUS_FMT_Y10_1X10, 10 },
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};
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static const struct csiphy_format csiphy_formats_sdm845[] = {
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{ MEDIA_BUS_FMT_UYVY8_2X8, 8 },
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{ MEDIA_BUS_FMT_VYUY8_2X8, 8 },
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{ MEDIA_BUS_FMT_YUYV8_2X8, 8 },
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{ MEDIA_BUS_FMT_YVYU8_2X8, 8 },
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{ MEDIA_BUS_FMT_SBGGR8_1X8, 8 },
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{ MEDIA_BUS_FMT_SGBRG8_1X8, 8 },
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{ MEDIA_BUS_FMT_SGRBG8_1X8, 8 },
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{ MEDIA_BUS_FMT_SRGGB8_1X8, 8 },
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{ MEDIA_BUS_FMT_SBGGR10_1X10, 10 },
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{ MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
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{ MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
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{ MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
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{ MEDIA_BUS_FMT_SBGGR12_1X12, 12 },
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{ MEDIA_BUS_FMT_SGBRG12_1X12, 12 },
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{ MEDIA_BUS_FMT_SGRBG12_1X12, 12 },
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{ MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
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{ MEDIA_BUS_FMT_SBGGR14_1X14, 14 },
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{ MEDIA_BUS_FMT_SGBRG14_1X14, 14 },
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{ MEDIA_BUS_FMT_SGRBG14_1X14, 14 },
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{ MEDIA_BUS_FMT_SRGGB14_1X14, 14 },
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{ MEDIA_BUS_FMT_Y10_1X10, 10 },
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};
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/*
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* csiphy_get_bpp - map media bus format to bits per pixel
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* @formats: supported media bus formats array
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@ -253,16 +277,20 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
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return -EINVAL;
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}
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val = readl_relaxed(csiphy->base_clk_mux);
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if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) {
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val &= ~0xf0;
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val |= cfg->csid_id << 4;
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} else {
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val &= ~0xf;
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val |= cfg->csid_id;
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if (csiphy->base_clk_mux) {
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val = readl_relaxed(csiphy->base_clk_mux);
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if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) {
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val &= ~0xf0;
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val |= cfg->csid_id << 4;
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} else {
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val &= ~0xf;
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val |= cfg->csid_id;
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}
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writel_relaxed(val, csiphy->base_clk_mux);
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/* Enforce reg write ordering between clk mux & lane enabling */
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wmb();
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}
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writel_relaxed(val, csiphy->base_clk_mux);
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wmb();
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csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
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@ -553,6 +581,10 @@ int msm_csiphy_subdev_init(struct camss *camss,
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csiphy->ops = &csiphy_ops_3ph_1_0;
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csiphy->formats = csiphy_formats_8x96;
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csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96);
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} else if (camss->version == CAMSS_845) {
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csiphy->ops = &csiphy_ops_3ph_1_0;
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csiphy->formats = csiphy_formats_sdm845;
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csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845);
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} else {
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return -EINVAL;
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}
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@ -566,11 +598,17 @@ int msm_csiphy_subdev_init(struct camss *camss,
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return PTR_ERR(csiphy->base);
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}
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r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
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csiphy->base_clk_mux = devm_ioremap_resource(dev, r);
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if (IS_ERR(csiphy->base_clk_mux)) {
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dev_err(dev, "could not map memory\n");
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return PTR_ERR(csiphy->base_clk_mux);
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if (camss->version == CAMSS_8x16 ||
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camss->version == CAMSS_8x96) {
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r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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res->reg[1]);
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csiphy->base_clk_mux = devm_ioremap_resource(dev, r);
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if (IS_ERR(csiphy->base_clk_mux)) {
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dev_err(dev, "could not map memory\n");
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return PTR_ERR(csiphy->base_clk_mux);
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}
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} else {
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csiphy->base_clk_mux = NULL;
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}
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/* Interrupt */
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@ -465,6 +465,80 @@ static const struct resources vfe_res_660[] = {
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}
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};
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static const struct resources csiphy_res_845[] = {
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/* CSIPHY0 */
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{
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.regulator = { NULL },
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.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
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"cpas_ahb", "cphy_rx_src", "csiphy0",
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"csiphy0_timer_src", "csiphy0_timer" },
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.clock_rate = { { 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 19200000, 240000000, 269333333 } },
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.reg = { "csiphy0" },
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.interrupt = { "csiphy0" }
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},
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/* CSIPHY1 */
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{
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.regulator = { NULL },
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.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
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"cpas_ahb", "cphy_rx_src", "csiphy1",
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"csiphy1_timer_src", "csiphy1_timer" },
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.clock_rate = { { 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 19200000, 240000000, 269333333 } },
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.reg = { "csiphy1" },
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.interrupt = { "csiphy1" }
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},
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/* CSIPHY2 */
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{
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.regulator = { NULL },
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.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
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"cpas_ahb", "cphy_rx_src", "csiphy2",
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"csiphy2_timer_src", "csiphy2_timer" },
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.clock_rate = { { 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 0 },
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{ 19200000, 240000000, 269333333 } },
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.reg = { "csiphy2" },
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.interrupt = { "csiphy2" }
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},
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/* CSIPHY3 */
|
||||
{
|
||||
.regulator = { NULL },
|
||||
.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
|
||||
"cpas_ahb", "cphy_rx_src", "csiphy3",
|
||||
"csiphy3_timer_src", "csiphy3_timer" },
|
||||
.clock_rate = { { 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 19200000, 240000000, 269333333 } },
|
||||
.reg = { "csiphy3" },
|
||||
.interrupt = { "csiphy3" }
|
||||
}
|
||||
};
|
||||
|
||||
static const struct resources csid_res_845[] = {
|
||||
/* CSID0 */
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue