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Merge drm/drm-next into drm-misc-next

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Backmerging to get new regmap APIs of v5.19-rc1.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
This commit is contained in:
Thomas Zimmermann 2022-06-20 18:21:25 +02:00
commit 2b1333b808
12469 changed files with 1020421 additions and 244432 deletions
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2
include/acpi/acbuffer.h
View file

@ -3,7 +3,7 @@
*
* Name: acbuffer.h - Support for buffers returned by ACPI predefined names
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/acconfig.h
View file

@ -3,7 +3,7 @@
*
* Name: acconfig.h - Global configuration constants
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/acexcep.h
View file

@ -3,7 +3,7 @@
*
* Name: acexcep.h - Exception codes returned by the ACPI subsystem
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/acnames.h
View file

@ -3,7 +3,7 @@
*
* Name: acnames.h - Global names and strings
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/acoutput.h
View file

@ -3,7 +3,7 @@
*
* Name: acoutput.h -- debug output
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/acpi.h
View file

@ -3,7 +3,7 @@
*
* Name: acpi.h - Master public include file used to interface to ACPICA
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

15
include/acpi/acpi_bus.h
View file

@ -481,6 +481,8 @@ void acpi_initialize_hp_context(struct acpi_device *adev,
extern struct bus_type acpi_bus_type;
int acpi_bus_for_each_dev(int (*fn)(struct device *, void *), void *data);
int acpi_dev_for_each_child(struct acpi_device *adev,
int (*fn)(struct acpi_device *, void *), void *data);
/*
* Events
@ -522,6 +524,7 @@ int acpi_device_fix_up_power(struct acpi_device *device);
int acpi_bus_update_power(acpi_handle handle, int *state_p);
int acpi_device_update_power(struct acpi_device *device, int *state_p);
bool acpi_bus_power_manageable(acpi_handle handle);
void acpi_dev_power_up_children_with_adr(struct acpi_device *adev);
int acpi_device_power_add_dependent(struct acpi_device *adev,
struct device *dev);
void acpi_device_power_remove_dependent(struct acpi_device *adev,
@ -582,14 +585,22 @@ int unregister_acpi_bus_type(struct acpi_bus_type *);
int acpi_bind_one(struct device *dev, struct acpi_device *adev);
int acpi_unbind_one(struct device *dev);
enum acpi_bridge_type {
ACPI_BRIDGE_TYPE_PCIE = 1,
ACPI_BRIDGE_TYPE_CXL,
};
struct acpi_pci_root {
struct acpi_device * device;
struct pci_bus *bus;
u16 segment;
int bridge_type;
struct resource secondary; /* downstream bus range */
u32 osc_support_set; /* _OSC state of support bits */
u32 osc_control_set; /* _OSC state of control bits */
u32 osc_support_set; /* _OSC state of support bits */
u32 osc_control_set; /* _OSC state of control bits */
u32 osc_ext_support_set; /* _OSC state of extended support bits */
u32 osc_ext_control_set; /* _OSC state of extended control bits */
phys_addr_t mcfg_addr;
};

2
include/acpi/acpiosxf.h
View file

@ -5,7 +5,7 @@
* interfaces must be implemented by OSL to interface the
* ACPI components to the host operating system.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

4
include/acpi/acpixf.h
View file

@ -3,7 +3,7 @@
*
* Name: acpixf.h - External interfaces to the ACPI subsystem
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
@ -12,7 +12,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20211217
#define ACPI_CA_VERSION 0x20220331
#include <acpi/acconfig.h>
#include <acpi/actypes.h>

2
include/acpi/acrestyp.h
View file

@ -3,7 +3,7 @@
*
* Name: acrestyp.h - Defines, types, and structures for resource descriptors
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/actbl.h
View file

@ -3,7 +3,7 @@
*
* Name: actbl.h - Basic ACPI Table Definitions
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

18
include/acpi/actbl1.h
View file

@ -3,7 +3,7 @@
*
* Name: actbl1.h - Additional ACPI table definitions
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
@ -373,17 +373,21 @@ struct acpi_cedt_cfmws {
u32 interleave_targets[];
};
struct acpi_cedt_cfmws_target_element {
u32 interleave_target;
};
/* Values for Interleave Arithmetic field above */
#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
/* Values for Restrictions field above */
#define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1)
#define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1<<1)
#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2)
#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
#define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1)
#define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1<<1)
#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2)
#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
/*******************************************************************************
*

175
include/acpi/actbl2.h
View file

@ -3,7 +3,7 @@
*
* Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
@ -25,6 +25,7 @@
* the wrong signature.
*/
#define ACPI_SIG_AGDI "AGDI" /* Arm Generic Diagnostic Dump and Reset Device Interface */
#define ACPI_SIG_APMT "APMT" /* Arm Performance Monitoring Unit table */
#define ACPI_SIG_BDAT "BDAT" /* BIOS Data ACPI Table */
#define ACPI_SIG_IORT "IORT" /* IO Remapping Table */
#define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */
@ -258,6 +259,85 @@ struct acpi_table_agdi {
#define ACPI_AGDI_SIGNALING_MODE (1)
/*******************************************************************************
*
* APMT - ARM Performance Monitoring Unit Table
*
* Conforms to:
* ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document
* ARM DEN0117 v1.0 November 25, 2021
*
******************************************************************************/
struct acpi_table_apmt {
struct acpi_table_header header; /* Common ACPI table header */
};
#define ACPI_APMT_NODE_ID_LENGTH 4
/*
* APMT subtables
*/
struct acpi_apmt_node {
u16 length;
u8 flags;
u8 type;
u32 id;
u64 inst_primary;
u32 inst_secondary;
u64 base_address0;
u64 base_address1;
u32 ovflw_irq;
u32 reserved;
u32 ovflw_irq_flags;
u32 proc_affinity;
u32 impl_id;
};
/* Masks for Flags field above */
#define ACPI_APMT_FLAGS_DUAL_PAGE (1<<0)
#define ACPI_APMT_FLAGS_AFFINITY (1<<1)
#define ACPI_APMT_FLAGS_ATOMIC (1<<2)
/* Values for Flags dual page field above */
#define ACPI_APMT_FLAGS_DUAL_PAGE_NSUPP (0<<0)
#define ACPI_APMT_FLAGS_DUAL_PAGE_SUPP (1<<0)
/* Values for Flags processor affinity field above */
#define ACPI_APMT_FLAGS_AFFINITY_PROC (0<<1)
#define ACPI_APMT_FLAGS_AFFINITY_PROC_CONTAINER (1<<1)
/* Values for Flags 64-bit atomic field above */
#define ACPI_APMT_FLAGS_ATOMIC_NSUPP (0<<2)
#define ACPI_APMT_FLAGS_ATOMIC_SUPP (1<<2)
/* Values for Type field above */
enum acpi_apmt_node_type {
ACPI_APMT_NODE_TYPE_MC = 0x00,
ACPI_APMT_NODE_TYPE_SMMU = 0x01,
ACPI_APMT_NODE_TYPE_PCIE_ROOT = 0x02,
ACPI_APMT_NODE_TYPE_ACPI = 0x03,
ACPI_APMT_NODE_TYPE_CACHE = 0x04,
ACPI_APMT_NODE_TYPE_COUNT
};
/* Masks for ovflw_irq_flags field above */
#define ACPI_APMT_OVFLW_IRQ_FLAGS_MODE (1<<0)
#define ACPI_APMT_OVFLW_IRQ_FLAGS_TYPE (1<<1)
/* Values for ovflw_irq_flags mode field above */
#define ACPI_APMT_OVFLW_IRQ_FLAGS_MODE_LEVEL (0<<0)
#define ACPI_APMT_OVFLW_IRQ_FLAGS_MODE_EDGE (1<<0)
/* Values for ovflw_irq_flags type field above */
#define ACPI_APMT_OVFLW_IRQ_FLAGS_TYPE_WIRED (0<<1)
/*******************************************************************************
*
* BDAT - BIOS Data ACPI Table
@ -277,7 +357,7 @@ struct acpi_table_bdat {
* IORT - IO Remapping Table
*
* Conforms to "IO Remapping Table System Software on ARM Platforms",
* Document number: ARM DEN 0049E.b, Feb 2021
* Document number: ARM DEN 0049E.d, Feb 2022
*
******************************************************************************/
@ -374,7 +454,8 @@ struct acpi_iort_root_complex {
u32 ats_attribute;
u32 pci_segment_number;
u8 memory_address_limit; /* Memory address size limit */
u8 reserved[3]; /* Reserved, must be zero */
u16 pasid_capabilities; /* PASID Capabilities */
u8 reserved[1]; /* Reserved, must be zero */
};
/* Masks for ats_attribute field above */
@ -383,6 +464,9 @@ struct acpi_iort_root_complex {
#define ACPI_IORT_PRI_SUPPORTED (1<<1) /* The root complex PRI support */
#define ACPI_IORT_PASID_FWD_SUPPORTED (1<<2) /* The root complex PASID forward support */
/* Masks for pasid_capabilities field above */
#define ACPI_IORT_PASID_MAX_WIDTH (0x1F) /* Bits 0-4 */
struct acpi_iort_smmu {
u64 base_address; /* SMMU base address */
u64 span; /* Length of memory range */
@ -458,6 +542,25 @@ struct acpi_iort_rmr {
u32 rmr_offset;
};
/* Masks for Flags field above */
#define ACPI_IORT_RMR_REMAP_PERMITTED (1)
#define ACPI_IORT_RMR_ACCESS_PRIVILEGE (1<<1)
/*
* Macro to access the Access Attributes in flags field above:
* Access Attributes is encoded in bits 9:2
*/
#define ACPI_IORT_RMR_ACCESS_ATTRIBUTES(flags) (((flags) >> 2) & 0xFF)
/* Values for above Access Attributes */
#define ACPI_IORT_RMR_ATTR_DEVICE_NGNRNE 0x00
#define ACPI_IORT_RMR_ATTR_DEVICE_NGNRE 0x01
#define ACPI_IORT_RMR_ATTR_DEVICE_NGRE 0x02
#define ACPI_IORT_RMR_ATTR_DEVICE_GRE 0x03
#define ACPI_IORT_RMR_ATTR_NORMAL_NC 0x04
#define ACPI_IORT_RMR_ATTR_NORMAL_IWB_OWB 0x05
struct acpi_iort_rmr_desc {
u64 base_address;
u64 length;
@ -762,7 +865,8 @@ enum acpi_madt_type {
ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
ACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,
ACPI_MADT_TYPE_RESERVED = 17 /* 17 and greater are reserved */
ACPI_MADT_TYPE_RESERVED = 17, /* 17 to 0x7F are reserved */
ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */
};
/*
@ -978,8 +1082,8 @@ struct acpi_madt_multiproc_wakeup {
u64 base_address;
};
#define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032
#define ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048
#define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032
#define ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048
struct acpi_madt_multiproc_wakeup_mailbox {
u16 command;
@ -992,6 +1096,12 @@ struct acpi_madt_multiproc_wakeup_mailbox {
#define ACPI_MP_WAKE_COMMAND_WAKEUP 1
/* 17: OEM data */
struct acpi_madt_oem_data {
u8 oem_data[0];
};
/*
* Common flags fields for MADT subtables
*/
@ -1597,7 +1707,7 @@ struct acpi_nhlt_mic_device_specific_config {
/* Values for array_type_ext above */
#define ACPI_NHLT_ARRAY_TYPE_RESERVED 0x09 // 9 and below are reserved
#define ACPI_NHLT_ARRAY_TYPE_RESERVED 0x09 /* 9 and below are reserved */
#define ACPI_NHLT_SMALL_LINEAR_2ELEMENT 0x0A
#define ACPI_NHLT_BIG_LINEAR_2ELEMENT 0x0B
#define ACPI_NHLT_FIRST_GEOMETRY_LINEAR_4ELEMENT 0x0C
@ -1617,17 +1727,17 @@ struct acpi_nhlt_vendor_mic_count {
struct acpi_nhlt_vendor_mic_config {
u8 type;
u8 panel;
u16 speaker_position_distance; // mm
u16 horizontal_offset; // mm
u16 vertical_offset; // mm
u8 frequency_low_band; // 5*hz
u8 frequency_high_band; // 500*hz
u16 direction_angle; // -180 - + 180
u16 elevation_angle; // -180 - + 180
u16 work_vertical_angle_begin; // -180 - + 180 with 2 deg step
u16 work_vertical_angle_end; // -180 - + 180 with 2 deg step
u16 work_horizontal_angle_begin; // -180 - + 180 with 2 deg step
u16 work_horizontal_angle_end; // -180 - + 180 with 2 deg step
u16 speaker_position_distance; /* mm */
u16 horizontal_offset; /* mm */
u16 vertical_offset; /* mm */
u8 frequency_low_band; /* 5*Hz */
u8 frequency_high_band; /* 500*Hz */
u16 direction_angle; /* -180 - + 180 */
u16 elevation_angle; /* -180 - + 180 */
u16 work_vertical_angle_begin; /* -180 - + 180 with 2 deg step */
u16 work_vertical_angle_end; /* -180 - + 180 with 2 deg step */
u16 work_horizontal_angle_begin; /* -180 - + 180 with 2 deg step */
u16 work_horizontal_angle_end; /* -180 - + 180 with 2 deg step */
};
/* Values for Type field above */
@ -1638,9 +1748,9 @@ struct acpi_nhlt_vendor_mic_config {
#define ACPI_NHLT_MIC_SUPER_CARDIOID 3
#define ACPI_NHLT_MIC_HYPER_CARDIOID 4
#define ACPI_NHLT_MIC_8_SHAPED 5
#define ACPI_NHLT_MIC_RESERVED6 6 // 6 is reserved
#define ACPI_NHLT_MIC_RESERVED6 6 /* 6 is reserved */
#define ACPI_NHLT_MIC_VENDOR_DEFINED 7
#define ACPI_NHLT_MIC_RESERVED 8 // 8 and above are reserved
#define ACPI_NHLT_MIC_RESERVED 8 /* 8 and above are reserved */
/* Values for Panel field above */
@ -1650,12 +1760,12 @@ struct acpi_nhlt_vendor_mic_config {
#define ACPI_NHLT_MIC_POSITION_RIGHT 3
#define ACPI_NHLT_MIC_POSITION_FRONT 4
#define ACPI_NHLT_MIC_POSITION_BACK 5
#define ACPI_NHLT_MIC_POSITION_RESERVED 6 // 6 and above are reserved
#define ACPI_NHLT_MIC_POSITION_RESERVED 6 /* 6 and above are reserved */
struct acpi_nhlt_vendor_mic_device_specific_config {
struct acpi_nhlt_mic_device_specific_config mic_array_device_config;
u8 number_of_microphones;
struct acpi_nhlt_vendor_mic_config mic_config[]; // indexed by number_of_microphones
struct acpi_nhlt_vendor_mic_config mic_config[]; /* Indexed by number_of_microphones */
};
/* Microphone SNR and Sensitivity extension */
@ -1668,32 +1778,23 @@ struct acpi_nhlt_mic_snr_sensitivity_extension {
/* Render device with feedback */
struct acpi_nhlt_render_feedback_device_specific_config {
u8 feedback_virtual_slot; // render slot in case of capture
u16 feedback_channels; // informative only
u8 feedback_virtual_slot; /* Render slot in case of capture */
u16 feedback_channels; /* Informative only */
u16 feedback_valid_bits_per_sample;
};
/* Linux-specific structures */
/* Non documented structures */
struct acpi_nhlt_linux_specific_count {
struct acpi_nhlt_device_info_count {
u8 structure_count;
};
struct acpi_nhlt_linux_specific_data {
struct acpi_nhlt_device_info {
u8 device_id[16];
u8 device_instance_id;
u8 device_port_id;
};
struct acpi_nhlt_linux_specific_data_b {
u8 specific_data[18];
};
struct acpi_nhlt_table_terminator {
u32 terminator_value;
u32 terminator_signature;
};
/*******************************************************************************
*
* PCCT - Platform Communications Channel Table (ACPI 5.0)
@ -2319,7 +2420,7 @@ struct acpi_table_rgrt {
u16 version;
u8 image_type;
u8 reserved;
u8 image[0];
u8 image[];
};
/* image_type values */

2
include/acpi/actbl3.h
View file

@ -3,7 +3,7 @@
*
* Name: actbl3.h - ACPI Table Definitions
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

19
include/acpi/actypes.h
View file

@ -3,7 +3,7 @@
*
* Name: actypes.h - Common data types for the entire ACPI subsystem
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
@ -539,14 +539,14 @@ typedef u64 acpi_integer;
* Can be used with access_width of struct acpi_generic_address and access_size of
* struct acpi_resource_generic_register.
*/
#define ACPI_ACCESS_BIT_SHIFT 2
#define ACPI_ACCESS_BYTE_SHIFT -1
#define ACPI_ACCESS_BIT_MAX (31 - ACPI_ACCESS_BIT_SHIFT)
#define ACPI_ACCESS_BYTE_MAX (31 - ACPI_ACCESS_BYTE_SHIFT)
#define ACPI_ACCESS_BIT_DEFAULT (8 - ACPI_ACCESS_BIT_SHIFT)
#define ACPI_ACCESS_BYTE_DEFAULT (8 - ACPI_ACCESS_BYTE_SHIFT)
#define ACPI_ACCESS_BIT_WIDTH(size) (1 << ((size) + ACPI_ACCESS_BIT_SHIFT))
#define ACPI_ACCESS_BYTE_WIDTH(size) (1 << ((size) + ACPI_ACCESS_BYTE_SHIFT))
#define ACPI_ACCESS_BIT_SHIFT 2
#define ACPI_ACCESS_BYTE_SHIFT -1
#define ACPI_ACCESS_BIT_MAX (31 - ACPI_ACCESS_BIT_SHIFT)
#define ACPI_ACCESS_BYTE_MAX (31 - ACPI_ACCESS_BYTE_SHIFT)
#define ACPI_ACCESS_BIT_DEFAULT (8 - ACPI_ACCESS_BIT_SHIFT)
#define ACPI_ACCESS_BYTE_DEFAULT (8 - ACPI_ACCESS_BYTE_SHIFT)
#define ACPI_ACCESS_BIT_WIDTH(size) (1 << ((size) + ACPI_ACCESS_BIT_SHIFT))
#define ACPI_ACCESS_BYTE_WIDTH(size) (1 << ((size) + ACPI_ACCESS_BYTE_SHIFT))
/*******************************************************************************
*
@ -1303,6 +1303,7 @@ typedef enum {
#define ACPI_OSI_WIN_10_RS5 0x13
#define ACPI_OSI_WIN_10_19H1 0x14
#define ACPI_OSI_WIN_10_20H1 0x15
#define ACPI_OSI_WIN_11 0x16
/* Definitions of getopt */

2
include/acpi/acuuid.h
View file

@ -3,7 +3,7 @@
*
* Name: acuuid.h - ACPI-related UUID/GUID definitions
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/apei.h
View file

@ -46,6 +46,8 @@ int erst_get_record_id_next(int *pos, u64 *record_id);
void erst_get_record_id_end(void);
ssize_t erst_read(u64 record_id, struct cper_record_header *record,
size_t buflen);
ssize_t erst_read_record(u64 record_id, struct cper_record_header *record,
size_t buflen, size_t recordlen, const guid_t *creatorid);
int erst_clear(u64 record_id);
int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data);

5
include/acpi/cppc_acpi.h
View file

@ -141,6 +141,7 @@ extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
extern int cppc_set_enable(int cpu, bool enable);
extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
extern bool acpi_cpc_valid(void);
extern bool cppc_allow_fast_switch(void);
extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data);
extern unsigned int cppc_get_transition_latency(int cpu);
extern bool cpc_ffh_supported(void);
@ -175,6 +176,10 @@ static inline bool acpi_cpc_valid(void)
{
return false;
}
static inline bool cppc_allow_fast_switch(void)
{
return false;
}
static inline unsigned int cppc_get_transition_latency(int cpu)
{
return CPUFREQ_ETERNAL;

2
include/acpi/platform/acenv.h
View file

@ -3,7 +3,7 @@
*
* Name: acenv.h - Host and compiler configuration
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/acenvex.h
View file

@ -3,7 +3,7 @@
*
* Name: acenvex.h - Extra host and compiler configuration
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/acgcc.h
View file

@ -3,7 +3,7 @@
*
* Name: acgcc.h - GCC specific defines, etc.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/acgccex.h
View file

@ -3,7 +3,7 @@
*
* Name: acgccex.h - Extra GCC specific defines, etc.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/acintel.h
View file

@ -3,7 +3,7 @@
*
* Name: acintel.h - VC specific defines, etc.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/aclinux.h
View file

@ -3,7 +3,7 @@
*
* Name: aclinux.h - OS specific defines, etc. for Linux
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

2
include/acpi/platform/aclinuxex.h
View file

@ -3,7 +3,7 @@
*
* Name: aclinuxex.h - Extra OS specific defines, etc. for Linux
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

1
include/asm-generic/Kbuild
View file

@ -44,6 +44,7 @@ mandatory-y += msi.h
mandatory-y += pci.h
mandatory-y += percpu.h
mandatory-y += pgalloc.h
mandatory-y += platform-feature.h
mandatory-y += preempt.h
mandatory-y += rwonce.h
mandatory-y += sections.h

113
include/asm-generic/compat.h
View file

@ -2,6 +2,25 @@
#ifndef __ASM_GENERIC_COMPAT_H
#define __ASM_GENERIC_COMPAT_H
#ifndef COMPAT_USER_HZ
#define COMPAT_USER_HZ 100
#endif
#ifndef COMPAT_RLIM_INFINITY
#define COMPAT_RLIM_INFINITY 0xffffffff
#endif
#ifndef COMPAT_OFF_T_MAX
#define COMPAT_OFF_T_MAX 0x7fffffff
#endif
#if !defined(compat_arg_u64) && !defined(CONFIG_CPU_BIG_ENDIAN)
#define compat_arg_u64(name) u32 name##_lo, u32 name##_hi
#define compat_arg_u64_dual(name) u32, name##_lo, u32, name##_hi
#define compat_arg_u64_glue(name) (((u64)name##_lo & 0xffffffffUL) | \
((u64)name##_hi << 32))
#endif
/* These types are common across all compat ABIs */
typedef u32 compat_size_t;
typedef s32 compat_ssize_t;
@ -24,6 +43,11 @@ typedef u32 compat_caddr_t;
typedef u32 compat_aio_context_t;
typedef u32 compat_old_sigset_t;
#ifndef __compat_uid_t
typedef u32 __compat_uid_t;
typedef u32 __compat_gid_t;
#endif
#ifndef __compat_uid32_t
typedef u32 __compat_uid32_t;
typedef u32 __compat_gid32_t;
@ -47,4 +71,93 @@ typedef u32 compat_sigset_word;
#define _COMPAT_NSIG_BPW 32
#endif
#ifndef compat_dev_t
typedef u32 compat_dev_t;
#endif
#ifndef compat_ipc_pid_t
typedef s32 compat_ipc_pid_t;
#endif
#ifndef compat_fsid_t
typedef __kernel_fsid_t compat_fsid_t;
#endif
#ifndef compat_statfs
struct compat_statfs {
compat_int_t f_type;
compat_int_t f_bsize;
compat_int_t f_blocks;
compat_int_t f_bfree;
compat_int_t f_bavail;
compat_int_t f_files;
compat_int_t f_ffree;
compat_fsid_t f_fsid;
compat_int_t f_namelen;
compat_int_t f_frsize;
compat_int_t f_flags;
compat_int_t f_spare[4];
};
#endif
#ifndef compat_ipc64_perm
struct compat_ipc64_perm {
compat_key_t key;
__compat_uid32_t uid;
__compat_gid32_t gid;
__compat_uid32_t cuid;
__compat_gid32_t cgid;
compat_mode_t mode;
unsigned char __pad1[4 - sizeof(compat_mode_t)];
compat_ushort_t seq;
compat_ushort_t __pad2;
compat_ulong_t unused1;
compat_ulong_t unused2;
};
struct compat_semid64_ds {
struct compat_ipc64_perm sem_perm;
compat_ulong_t sem_otime;
compat_ulong_t sem_otime_high;
compat_ulong_t sem_ctime;
compat_ulong_t sem_ctime_high;
compat_ulong_t sem_nsems;
compat_ulong_t __unused3;
compat_ulong_t __unused4;
};
struct compat_msqid64_ds {
struct compat_ipc64_perm msg_perm;
compat_ulong_t msg_stime;
compat_ulong_t msg_stime_high;
compat_ulong_t msg_rtime;
compat_ulong_t msg_rtime_high;
compat_ulong_t msg_ctime;
compat_ulong_t msg_ctime_high;
compat_ulong_t msg_cbytes;
compat_ulong_t msg_qnum;
compat_ulong_t msg_qbytes;
compat_pid_t msg_lspid;
compat_pid_t msg_lrpid;
compat_ulong_t __unused4;
compat_ulong_t __unused5;
};
struct compat_shmid64_ds {
struct compat_ipc64_perm shm_perm;
compat_size_t shm_segsz;
compat_ulong_t shm_atime;
compat_ulong_t shm_atime_high;
compat_ulong_t shm_dtime;
compat_ulong_t shm_dtime_high;
compat_ulong_t shm_ctime;
compat_ulong_t shm_ctime_high;
compat_pid_t shm_cpid;
compat_pid_t shm_lpid;
compat_ulong_t shm_nattch;
compat_ulong_t __unused4;
compat_ulong_t __unused5;
};
#endif
#endif

22
include/asm-generic/export.h
View file

@ -2,6 +2,14 @@
#ifndef __ASM_GENERIC_EXPORT_H
#define __ASM_GENERIC_EXPORT_H
/*
* This comment block is used by fixdep. Please do not remove.
*
* When CONFIG_MODVERSIONS is changed from n to y, all source files having
* EXPORT_SYMBOL variants must be re-compiled because genksyms is run as a
* side effect of the *.o build rule.
*/
#ifndef KSYM_FUNC
#define KSYM_FUNC(x) x
#endif
@ -12,9 +20,6 @@
#else
#define KSYM_ALIGN 4
#endif
#ifndef KCRC_ALIGN
#define KCRC_ALIGN 4
#endif
.macro __put, val, name
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
@ -43,17 +48,6 @@ __ksymtab_\name:
__kstrtab_\name:
.asciz "\name"
.previous
#ifdef CONFIG_MODVERSIONS
.section ___kcrctab\sec+\name,"a"
.balign KCRC_ALIGN
#if defined(CONFIG_MODULE_REL_CRCS)
.long __crc_\name - .
#else
.long __crc_\name
#endif
.weak __crc_\name
.previous
#endif
#endif
.endm

28
include/asm-generic/hugetlb.h
View file

@ -2,6 +2,9 @@
#ifndef _ASM_GENERIC_HUGETLB_H
#define _ASM_GENERIC_HUGETLB_H
#include <linux/swap.h>
#include <linux/swapops.h>
static inline pte_t mk_huge_pte(struct page *page, pgprot_t pgprot)
{
return mk_pte(page, pgprot);
@ -32,6 +35,21 @@ static inline pte_t huge_pte_modify(pte_t pte, pgprot_t newprot)
return pte_modify(pte, newprot);
}
static inline pte_t huge_pte_mkuffd_wp(pte_t pte)
{
return pte_mkuffd_wp(pte);
}
static inline pte_t huge_pte_clear_uffd_wp(pte_t pte)
{
return pte_clear_uffd_wp(pte);
}
static inline int huge_pte_uffd_wp(pte_t pte)
{
return pte_uffd_wp(pte);
}
#ifndef __HAVE_ARCH_HUGE_PTE_CLEAR
static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long sz)
@ -66,10 +84,10 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
static inline pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
ptep_clear_flush(vma, addr, ptep);
return ptep_clear_flush(vma, addr, ptep);
}
#endif
@ -80,6 +98,12 @@ static inline int huge_pte_none(pte_t pte)
}
#endif
/* Please refer to comments above pte_none_mostly() for the usage */
static inline int huge_pte_none_mostly(pte_t pte)
{
return huge_pte_none(pte) || is_pte_marker(pte);
}
#ifndef __HAVE_ARCH_HUGE_PTE_WRPROTECT
static inline pte_t huge_pte_wrprotect(pte_t pte)
{

2
include/asm-generic/pgtable-nopmd.h
View file

@ -30,6 +30,8 @@ typedef struct { pud_t pud; } pmd_t;
static inline int pud_none(pud_t pud) { return 0; }
static inline int pud_bad(pud_t pud) { return 0; }
static inline int pud_present(pud_t pud) { return 1; }
static inline int pud_user(pud_t pud) { return 0; }
static inline int pud_leaf(pud_t pud) { return 0; }
static inline void pud_clear(pud_t *pud) { }
#define pmd_ERROR(pmd) (pud_ERROR((pmd).pud))

8
include/asm-generic/platform-feature.h Normal file
View file

@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_GENERIC_PLATFORM_FEATURE_H
#define _ASM_GENERIC_PLATFORM_FEATURE_H
/* Number of arch specific feature flags. */
#define PLATFORM_ARCH_FEAT_N 0
#endif /* _ASM_GENERIC_PLATFORM_FEATURE_H */

32
include/asm-generic/qrwlock.h
View file

@ -2,6 +2,10 @@
/*
* Queue read/write lock
*
* These use generic atomic and locking routines, but depend on a fair spinlock
* implementation in order to be fair themselves. The implementation in
* asm-generic/spinlock.h meets these requirements.
*
* (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.
*
* Authors: Waiman Long <waiman.long@hp.com>
@ -33,8 +37,8 @@ extern void queued_read_lock_slowpath(struct qrwlock *lock);
extern void queued_write_lock_slowpath(struct qrwlock *lock);
/**
* queued_read_trylock - try to acquire read lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* queued_read_trylock - try to acquire read lock of a queued rwlock
* @lock : Pointer to queued rwlock structure
* Return: 1 if lock acquired, 0 if failed
*/
static inline int queued_read_trylock(struct qrwlock *lock)
@ -52,8 +56,8 @@ static inline int queued_read_trylock(struct qrwlock *lock)
}
/**
* queued_write_trylock - try to acquire write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* queued_write_trylock - try to acquire write lock of a queued rwlock
* @lock : Pointer to queued rwlock structure
* Return: 1 if lock acquired, 0 if failed
*/
static inline int queued_write_trylock(struct qrwlock *lock)
@ -68,8 +72,8 @@ static inline int queued_write_trylock(struct qrwlock *lock)
_QW_LOCKED));
}
/**
* queued_read_lock - acquire read lock of a queue rwlock
* @lock: Pointer to queue rwlock structure
* queued_read_lock - acquire read lock of a queued rwlock
* @lock: Pointer to queued rwlock structure
*/
static inline void queued_read_lock(struct qrwlock *lock)
{
@ -84,8 +88,8 @@ static inline void queued_read_lock(struct qrwlock *lock)
}
/**
* queued_write_lock - acquire write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* queued_write_lock - acquire write lock of a queued rwlock
* @lock : Pointer to queued rwlock structure
*/
static inline void queued_write_lock(struct qrwlock *lock)
{
@ -98,8 +102,8 @@ static inline void queued_write_lock(struct qrwlock *lock)
}
/**
* queued_read_unlock - release read lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* queued_read_unlock - release read lock of a queued rwlock
* @lock : Pointer to queued rwlock structure
*/
static inline void queued_read_unlock(struct qrwlock *lock)
{
@ -110,8 +114,8 @@ static inline void queued_read_unlock(struct qrwlock *lock)
}
/**
* queued_write_unlock - release write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* queued_write_unlock - release write lock of a queued rwlock
* @lock : Pointer to queued rwlock structure
*/
static inline void queued_write_unlock(struct qrwlock *lock)
{
@ -120,7 +124,7 @@ static inline void queued_write_unlock(struct qrwlock *lock)
/**
* queued_rwlock_is_contended - check if the lock is contended
* @lock : Pointer to queue rwlock structure
* @lock : Pointer to queued rwlock structure
* Return: 1 if lock contended, 0 otherwise
*/
static inline int queued_rwlock_is_contended(struct qrwlock *lock)
@ -130,7 +134,7 @@ static inline int queued_rwlock_is_contended(struct qrwlock *lock)
/*
* Remapping rwlock architecture specific functions to the corresponding
* queue rwlock functions.
* queued rwlock functions.
*/
#define arch_read_lock(l) queued_read_lock(l)
#define arch_write_lock(l) queued_write_lock(l)

2
include/asm-generic/qrwlock_types.h
View file

@ -7,7 +7,7 @@
#include <asm/spinlock_types.h>
/*
* The queue read/write lock data structure
* The queued read/write lock data structure
*/
typedef struct qrwlock {

29
include/asm-generic/qspinlock.h
View file

@ -2,6 +2,35 @@
/*
* Queued spinlock
*
* A 'generic' spinlock implementation that is based on MCS locks. For an
* architecture that's looking for a 'generic' spinlock, please first consider
* ticket-lock.h and only come looking here when you've considered all the
* constraints below and can show your hardware does actually perform better
* with qspinlock.
*
* qspinlock relies on atomic_*_release()/atomic_*_acquire() to be RCsc (or no
* weaker than RCtso if you're power), where regular code only expects atomic_t
* to be RCpc.
*
* qspinlock relies on a far greater (compared to asm-generic/spinlock.h) set
* of atomic operations to behave well together, please audit them carefully to
* ensure they all have forward progress. Many atomic operations may default to
* cmpxchg() loops which will not have good forward progress properties on
* LL/SC architectures.
*
* One notable example is atomic_fetch_or_acquire(), which x86 cannot (cheaply)
* do. Carefully read the patches that introduced
* queued_fetch_set_pending_acquire().
*
* qspinlock also heavily relies on mixed size atomic operations, in specific
* it requires architectures to have xchg16; something which many LL/SC
* architectures need to implement as a 32bit and+or in order to satisfy the
* forward progress guarantees mentioned above.
*
* Further reading on mixed size atomics that might be relevant:
*
* http://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf
*
* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
*

94
include/asm-generic/spinlock.h
View file

@ -1,12 +1,92 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* 'Generic' ticket-lock implementation.
*
* It relies on atomic_fetch_add() having well defined forward progress
* guarantees under contention. If your architecture cannot provide this, stick
* to a test-and-set lock.
*
* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
* sub-word of the value. This is generally true for anything LL/SC although
* you'd be hard pressed to find anything useful in architecture specifications
* about this. If your architecture cannot do this you might be better off with
* a test-and-set.
*
* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
* a full fence after the spin to upgrade the otherwise-RCpc
* atomic_cond_read_acquire().
*
* The implementation uses smp_cond_load_acquire() to spin, so if the
* architecture has WFE like instructions to sleep instead of poll for word
* modifications be sure to implement that (see ARM64 for example).
*
*/
#ifndef __ASM_GENERIC_SPINLOCK_H
#define __ASM_GENERIC_SPINLOCK_H
/*
* You need to implement asm/spinlock.h for SMP support. The generic
* version does not handle SMP.
*/
#ifdef CONFIG_SMP
#error need an architecture specific asm/spinlock.h
#endif
#include <linux/atomic.h>
#include <asm-generic/spinlock_types.h>
static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
{
u32 val = atomic_fetch_add(1<<16, lock);
u16 ticket = val >> 16;
if (ticket == (u16)val)
return;
/*
* atomic_cond_read_acquire() is RCpc, but rather than defining a
* custom cond_read_rcsc() here we just emit a full fence. We only
* need the prior reads before subsequent writes ordering from
* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
* have no outstanding writes due to the atomic_fetch_add() the extra
* orderings are free.
*/
atomic_cond_read_acquire(lock, ticket == (u16)VAL);
smp_mb();
}
static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
{
u32 old = atomic_read(lock);
if ((old >> 16) != (old & 0xffff))
return false;
return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
}
static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
{
u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
u32 val = atomic_read(lock);
smp_store_release(ptr, (u16)val + 1);
}
static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
u32 val = atomic_read(lock);
return ((val >> 16) != (val & 0xffff));
}
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
{
u32 val = atomic_read(lock);
return (s16)((val >> 16) - (val & 0xffff)) > 1;
}
static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
return !arch_spin_is_locked(&lock);
}
#include <asm/qrwlock.h>
#endif /* __ASM_GENERIC_SPINLOCK_H */

17
include/asm-generic/spinlock_types.h Normal file
View file

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
#define __ASM_GENERIC_SPINLOCK_TYPES_H
#include <linux/types.h>
typedef atomic_t arch_spinlock_t;
/*
* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
* include.
*/
#include <asm/qrwlock_types.h>
#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */

14
include/asm-generic/tlb.h
View file

@ -658,6 +658,20 @@ static inline void tlb_flush_p4d_range(struct mmu_gather *tlb,
} while (0)
#endif
#ifndef pte_needs_flush
static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
{
return true;
}
#endif
#ifndef huge_pmd_needs_flush
static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
{
return true;
}
#endif
#endif /* CONFIG_MMU */
#endif /* _ASM_GENERIC__TLB_H */

12
include/asm-generic/vmlinux.lds.h
View file

@ -126,13 +126,13 @@
*/
#define SCHED_DATA \
STRUCT_ALIGN(); \
__begin_sched_classes = .; \
*(__idle_sched_class) \
*(__fair_sched_class) \
*(__rt_sched_class) \
*(__dl_sched_class) \
__sched_class_highest = .; \
*(__stop_sched_class) \
__end_sched_classes = .;
*(__dl_sched_class) \
*(__rt_sched_class) \
*(__fair_sched_class) \
*(__idle_sched_class) \
__sched_class_lowest = .;
/* The actual configuration determine if the init/exit sections
* are handled as text/data or they can be discarded (which

31
include/clocksource/timer-goldfish.h Normal file
View file

@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* goldfish-timer clocksource
* Registers definition for the goldfish-timer device
*/
#ifndef _CLOCKSOURCE_TIMER_GOLDFISH_H
#define _CLOCKSOURCE_TIMER_GOLDFISH_H
/*
* TIMER_TIME_LOW get low bits of current time and update TIMER_TIME_HIGH
* TIMER_TIME_HIGH get high bits of time at last TIMER_TIME_LOW read
* TIMER_ALARM_LOW set low bits of alarm and activate it
* TIMER_ALARM_HIGH set high bits of next alarm
* TIMER_IRQ_ENABLED enable alarm interrupt
* TIMER_CLEAR_ALARM disarm an existing alarm
* TIMER_ALARM_STATUS alarm status (running or not)
* TIMER_CLEAR_INTERRUPT clear interrupt
*/
#define TIMER_TIME_LOW 0x00
#define TIMER_TIME_HIGH 0x04
#define TIMER_ALARM_LOW 0x08
#define TIMER_ALARM_HIGH 0x0c
#define TIMER_IRQ_ENABLED 0x10
#define TIMER_CLEAR_ALARM 0x14
#define TIMER_ALARM_STATUS 0x18
#define TIMER_CLEAR_INTERRUPT 0x1c
extern int goldfish_timer_init(int irq, void __iomem *base);
#endif /* _CLOCKSOURCE_TIMER_GOLDFISH_H */

73
include/clocksource/timer-xilinx.h Normal file
View file

@ -0,0 +1,73 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
*/
#ifndef XILINX_TIMER_H
#define XILINX_TIMER_H
#include <linux/compiler.h>
#define TCSR0 0x00
#define TLR0 0x04
#define TCR0 0x08
#define TCSR1 0x10
#define TLR1 0x14
#define TCR1 0x18
#define TCSR_MDT BIT(0)
#define TCSR_UDT BIT(1)
#define TCSR_GENT BIT(2)
#define TCSR_CAPT BIT(3)
#define TCSR_ARHT BIT(4)
#define TCSR_LOAD BIT(5)
#define TCSR_ENIT BIT(6)
#define TCSR_ENT BIT(7)
#define TCSR_TINT BIT(8)
#define TCSR_PWMA BIT(9)
#define TCSR_ENALL BIT(10)
#define TCSR_CASC BIT(11)
struct clk;
struct device_node;
struct regmap;
/**
* struct xilinx_timer_priv - Private data for Xilinx AXI timer drivers
* @map: Regmap of the device, possibly with an offset
* @clk: Parent clock
* @max: Maximum value of the counters
*/
struct xilinx_timer_priv {
struct regmap *map;
struct clk *clk;
u32 max;
};
/**
* xilinx_timer_tlr_cycles() - Calculate the TLR for a period specified
* in clock cycles
* @priv: The timer's private data
* @tcsr: The value of the TCSR register for this counter
* @cycles: The number of cycles in this period
*
* Callers of this function MUST ensure that @cycles is representable as
* a TLR.
*
* Return: The calculated value for TLR
*/
u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
u64 cycles);
/**
* xilinx_timer_get_period() - Get the current period of a counter
* @priv: The timer's private data
* @tlr: The value of TLR for this counter
* @tcsr: The value of TCSR for this counter
*
* Return: The period, in ns
*/
unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
u32 tlr, u32 tcsr);
#endif /* XILINX_TIMER_H */

4
include/crypto/sm4.h
View file

@ -21,6 +21,10 @@ struct sm4_ctx {
u32 rkey_dec[SM4_RKEY_WORDS];
};
extern const u32 crypto_sm4_fk[];
extern const u32 crypto_sm4_ck[];
extern const u8 crypto_sm4_sbox[];
/**
* sm4_expandkey - Expands the SM4 key as described in GB/T 32907-2016
* @ctx: The location where the computed key will be stored.

8
include/drm/drm_cache.h
View file

@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
* optimization entirely for ARM and arm64.
*/
return false;
#elif defined(CONFIG_LOONGARCH)
/*
* LoongArch maintains cache coherency in hardware, but its WUC attribute
* (Weak-ordered UnCached, which is similar to WC) is out of the scope of
* cache coherency machanism. This means WUC can only used for write-only
* memory regions.
*/
return false;
#else
return true;
#endif

6
include/drm/drm_edid.h
View file

@ -122,7 +122,7 @@ struct detailed_data_monitor_range {
u8 supported_scalings;
u8 preferred_refresh;
} __attribute__((packed)) cvt;
} formula;
} __attribute__((packed)) formula;
} __attribute__((packed));
struct detailed_data_wpindex {
@ -155,7 +155,7 @@ struct detailed_non_pixel {
struct detailed_data_wpindex color;
struct std_timing timings[6];
struct cvt_timing cvt[4];
} data;
} __attribute__((packed)) data;
} __attribute__((packed));
#define EDID_DETAIL_EST_TIMINGS 0xf7
@ -173,7 +173,7 @@ struct detailed_timing {
union {
struct detailed_pixel_timing pixel_data;
struct detailed_non_pixel other_data;
} data;
} __attribute__((packed)) data;
} __attribute__((packed));
#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)

7
include/drm/drm_panel.h
View file

@ -179,6 +179,13 @@ struct drm_panel {
* Panel entry in registry.
*/
struct list_head list;
/**
* @dsc:
*
* Panel DSC pps payload to be sent
*/
struct drm_dsc_config *dsc;
};
void drm_panel_init(struct drm_panel *panel, struct device *dev,

11
include/drm/drm_writeback.h
View file

@ -30,6 +30,8 @@ struct drm_writeback_connector {
* @drm_writeback_connector control the behaviour of the @encoder
* by passing the @enc_funcs parameter to drm_writeback_connector_init()
* function.
* For users of drm_writeback_connector_init_with_encoder(), this field
* is not valid as the encoder is managed within their drivers.
*/
struct drm_encoder encoder;
@ -150,7 +152,14 @@ int drm_writeback_connector_init(struct drm_device *dev,
struct drm_writeback_connector *wb_connector,
const struct drm_connector_funcs *con_funcs,
const struct drm_encoder_helper_funcs *enc_helper_funcs,
const u32 *formats, int n_formats);
const u32 *formats, int n_formats,
u32 possible_crtcs);
int drm_writeback_connector_init_with_encoder(struct drm_device *dev,
struct drm_writeback_connector *wb_connector,
struct drm_encoder *enc,
const struct drm_connector_funcs *con_funcs, const u32 *formats,
int n_formats);
int drm_writeback_set_fb(struct drm_connector_state *conn_state,
struct drm_framebuffer *fb);

31
include/drm/i915_pciids.h
View file

@ -683,4 +683,35 @@
INTEL_VGA_DEVICE(0xA78A, info), \
INTEL_VGA_DEVICE(0xA78B, info)
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
INTEL_VGA_DEVICE(0xA720, info), \
INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
INTEL_VGA_DEVICE(0xA7A1, info), \
INTEL_VGA_DEVICE(0xA7A8, info), \
INTEL_VGA_DEVICE(0xA7A9, info)
/* DG2 */
#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
INTEL_VGA_DEVICE(0x5692, info)
#define INTEL_DG2_G11_IDS(info) \
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
INTEL_VGA_DEVICE(0x56B0, info)
#define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
INTEL_VGA_DEVICE(0x5697, info), \
INTEL_VGA_DEVICE(0x56B2, info)
#define INTEL_DG2_IDS(info) \
INTEL_DG2_G10_IDS(info), \
INTEL_DG2_G11_IDS(info), \
INTEL_DG2_G12_IDS(info)
#endif /* _I915_PCIIDS_H */

17
include/dt-bindings/clock/en7523-clk.h Normal file
View file

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
#define EN7523_CLK_GSW 0
#define EN7523_CLK_EMI 1
#define EN7523_CLK_BUS 2
#define EN7523_CLK_SLIC 3
#define EN7523_CLK_SPI 4
#define EN7523_CLK_NPU 5
#define EN7523_CLK_CRYPTO 6
#define EN7523_CLK_PCIE 7
#define EN7523_NUM_CLOCKS 8
#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */

16
include/dt-bindings/clock/imx8mn-clock.h
View file

@ -243,6 +243,20 @@
#define IMX8MN_CLK_M7_CORE 221
#define IMX8MN_CLK_END 222
#define IMX8MN_CLK_GPT_3M 222
#define IMX8MN_CLK_GPT1 223
#define IMX8MN_CLK_GPT1_ROOT 224
#define IMX8MN_CLK_GPT2 225
#define IMX8MN_CLK_GPT2_ROOT 226
#define IMX8MN_CLK_GPT3 227
#define IMX8MN_CLK_GPT3_ROOT 228
#define IMX8MN_CLK_GPT4 229
#define IMX8MN_CLK_GPT4_ROOT 230
#define IMX8MN_CLK_GPT5 231
#define IMX8MN_CLK_GPT5_ROOT 232
#define IMX8MN_CLK_GPT6 233
#define IMX8MN_CLK_GPT6_ROOT 234
#define IMX8MN_CLK_END 235
#endif

9
include/dt-bindings/clock/imx8mp-clock.h
View file

@ -317,8 +317,15 @@
#define IMX8MP_CLK_AUDIO_AXI 310
#define IMX8MP_CLK_HSIO_AXI 311
#define IMX8MP_CLK_MEDIA_ISP 312
#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
#define IMX8MP_CLK_CLKOUT1_SEL 314
#define IMX8MP_CLK_CLKOUT1_DIV 315
#define IMX8MP_CLK_CLKOUT1 316
#define IMX8MP_CLK_CLKOUT2_SEL 317
#define IMX8MP_CLK_CLKOUT2_DIV 318
#define IMX8MP_CLK_CLKOUT2 319
#define IMX8MP_CLK_END 313
#define IMX8MP_CLK_END 320
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1

445
include/dt-bindings/clock/mt8186-clk.h Normal file
View file

@ -0,0 +1,445 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT8186_H
#define _DT_BINDINGS_CLK_MT8186_H
/* MCUSYS */
#define CLK_MCU_ARMPLL_LL_SEL 0
#define CLK_MCU_ARMPLL_BL_SEL 1
#define CLK_MCU_ARMPLL_BUS_SEL 2
#define CLK_MCU_NR_CLK 3
/* TOPCKGEN */
#define CLK_TOP_AXI 0
#define CLK_TOP_SCP 1
#define CLK_TOP_MFG 2
#define CLK_TOP_CAMTG 3
#define CLK_TOP_CAMTG1 4
#define CLK_TOP_CAMTG2 5
#define CLK_TOP_CAMTG3 6
#define CLK_TOP_CAMTG4 7
#define CLK_TOP_CAMTG5 8
#define CLK_TOP_CAMTG6 9
#define CLK_TOP_UART 10
#define CLK_TOP_SPI 11
#define CLK_TOP_MSDC50_0_HCLK 12
#define CLK_TOP_MSDC50_0 13
#define CLK_TOP_MSDC30_1 14
#define CLK_TOP_AUDIO 15
#define CLK_TOP_AUD_INTBUS 16
#define CLK_TOP_AUD_1 17
#define CLK_TOP_AUD_2 18
#define CLK_TOP_AUD_ENGEN1 19
#define CLK_TOP_AUD_ENGEN2 20
#define CLK_TOP_DISP_PWM 21
#define CLK_TOP_SSPM 22
#define CLK_TOP_DXCC 23
#define CLK_TOP_USB_TOP 24
#define CLK_TOP_SRCK 25
#define CLK_TOP_SPM 26
#define CLK_TOP_I2C 27
#define CLK_TOP_PWM 28
#define CLK_TOP_SENINF 29
#define CLK_TOP_SENINF1 30
#define CLK_TOP_SENINF2 31
#define CLK_TOP_SENINF3 32
#define CLK_TOP_AES_MSDCFDE 33
#define CLK_TOP_PWRAP_ULPOSC 34
#define CLK_TOP_CAMTM 35
#define CLK_TOP_VENC 36
#define CLK_TOP_CAM 37
#define CLK_TOP_IMG1 38
#define CLK_TOP_IPE 39
#define CLK_TOP_DPMAIF 40
#define CLK_TOP_VDEC 41
#define CLK_TOP_DISP 42
#define CLK_TOP_MDP 43
#define CLK_TOP_AUDIO_H 44
#define CLK_TOP_UFS 45
#define CLK_TOP_AES_FDE 46
#define CLK_TOP_AUDIODSP 47
#define CLK_TOP_DVFSRC 48
#define CLK_TOP_DSI_OCC 49
#define CLK_TOP_SPMI_MST 50
#define CLK_TOP_SPINOR 51
#define CLK_TOP_NNA 52
#define CLK_TOP_NNA1 53
#define CLK_TOP_NNA2 54
#define CLK_TOP_SSUSB_XHCI 55
#define CLK_TOP_SSUSB_TOP_1P 56
#define CLK_TOP_SSUSB_XHCI_1P 57
#define CLK_TOP_WPE 58
#define CLK_TOP_DPI 59
#define CLK_TOP_U3_OCC_250M 60
#define CLK_TOP_U3_OCC_500M 61
#define CLK_TOP_ADSP_BUS 62
#define CLK_TOP_APLL_I2S0_MCK_SEL 63
#define CLK_TOP_APLL_I2S1_MCK_SEL 64
#define CLK_TOP_APLL_I2S2_MCK_SEL 65
#define CLK_TOP_APLL_I2S4_MCK_SEL 66
#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67
#define CLK_TOP_MAINPLL_D2 68
#define CLK_TOP_MAINPLL_D2_D2 69
#define CLK_TOP_MAINPLL_D2_D4 70
#define CLK_TOP_MAINPLL_D2_D16 71
#define CLK_TOP_MAINPLL_D3 72
#define CLK_TOP_MAINPLL_D3_D2 73
#define CLK_TOP_MAINPLL_D3_D4 74
#define CLK_TOP_MAINPLL_D5 75
#define CLK_TOP_MAINPLL_D5_D2 76
#define CLK_TOP_MAINPLL_D5_D4 77
#define CLK_TOP_MAINPLL_D7 78
#define CLK_TOP_MAINPLL_D7_D2 79
#define CLK_TOP_MAINPLL_D7_D4 80
#define CLK_TOP_UNIVPLL 81
#define CLK_TOP_UNIVPLL_D2 82
#define CLK_TOP_UNIVPLL_D2_D2 83
#define CLK_TOP_UNIVPLL_D2_D4 84
#define CLK_TOP_UNIVPLL_D3 85
#define CLK_TOP_UNIVPLL_D3_D2 86
#define CLK_TOP_UNIVPLL_D3_D4 87
#define CLK_TOP_UNIVPLL_D3_D8 88
#define CLK_TOP_UNIVPLL_D3_D32 89
#define CLK_TOP_UNIVPLL_D5 90
#define CLK_TOP_UNIVPLL_D5_D2 91
#define CLK_TOP_UNIVPLL_D5_D4 92
#define CLK_TOP_UNIVPLL_D7 93
#define CLK_TOP_UNIVPLL_192M 94
#define CLK_TOP_UNIVPLL_192M_D4 95
#define CLK_TOP_UNIVPLL_192M_D8 96
#define CLK_TOP_UNIVPLL_192M_D16 97
#define CLK_TOP_UNIVPLL_192M_D32 98
#define CLK_TOP_APLL1_D2 99
#define CLK_TOP_APLL1_D4 100
#define CLK_TOP_APLL1_D8 101
#define CLK_TOP_APLL2_D2 102
#define CLK_TOP_APLL2_D4 103
#define CLK_TOP_APLL2_D8 104
#define CLK_TOP_MMPLL_D2 105
#define CLK_TOP_TVDPLL_D2 106
#define CLK_TOP_TVDPLL_D4 107
#define CLK_TOP_TVDPLL_D8 108
#define CLK_TOP_TVDPLL_D16 109
#define CLK_TOP_TVDPLL_D32 110
#define CLK_TOP_MSDCPLL_D2 111
#define CLK_TOP_ULPOSC1 112
#define CLK_TOP_ULPOSC1_D2 113
#define CLK_TOP_ULPOSC1_D4 114
#define CLK_TOP_ULPOSC1_D8 115
#define CLK_TOP_ULPOSC1_D10 116
#define CLK_TOP_ULPOSC1_D16 117
#define CLK_TOP_ULPOSC1_D32 118
#define CLK_TOP_ADSPPLL_D2 119
#define CLK_TOP_ADSPPLL_D4 120
#define CLK_TOP_ADSPPLL_D8 121
#define CLK_TOP_NNAPLL_D2 122
#define CLK_TOP_NNAPLL_D4 123
#define CLK_TOP_NNAPLL_D8 124
#define CLK_TOP_NNA2PLL_D2 125
#define CLK_TOP_NNA2PLL_D4 126
#define CLK_TOP_NNA2PLL_D8 127
#define CLK_TOP_F_BIST2FPC 128
#define CLK_TOP_466M_FMEM 129
#define CLK_TOP_MPLL 130
#define CLK_TOP_APLL12_CK_DIV0 131
#define CLK_TOP_APLL12_CK_DIV1 132
#define CLK_TOP_APLL12_CK_DIV2 133
#define CLK_TOP_APLL12_CK_DIV4 134
#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135
#define CLK_TOP_NR_CLK 136
/* INFRACFG_AO */
#define CLK_INFRA_AO_PMIC_TMR 0
#define CLK_INFRA_AO_PMIC_AP 1
#define CLK_INFRA_AO_PMIC_MD 2
#define CLK_INFRA_AO_PMIC_CONN 3
#define CLK_INFRA_AO_SCP_CORE 4
#define CLK_INFRA_AO_SEJ 5
#define CLK_INFRA_AO_APXGPT 6
#define CLK_INFRA_AO_ICUSB 7
#define CLK_INFRA_AO_GCE 8
#define CLK_INFRA_AO_THERM 9
#define CLK_INFRA_AO_I2C_AP 10
#define CLK_INFRA_AO_I2C_CCU 11
#define CLK_INFRA_AO_I2C_SSPM 12
#define CLK_INFRA_AO_I2C_RSV 13
#define CLK_INFRA_AO_PWM_HCLK 14
#define CLK_INFRA_AO_PWM1 15
#define CLK_INFRA_AO_PWM2 16
#define CLK_INFRA_AO_PWM3 17
#define CLK_INFRA_AO_PWM4 18
#define CLK_INFRA_AO_PWM5 19
#define CLK_INFRA_AO_PWM 20
#define CLK_INFRA_AO_UART0 21
#define CLK_INFRA_AO_UART1 22
#define CLK_INFRA_AO_UART2 23
#define CLK_INFRA_AO_GCE_26M 24
#define CLK_INFRA_AO_CQ_DMA_FPC 25
#define CLK_INFRA_AO_BTIF 26
#define CLK_INFRA_AO_SPI0 27
#define CLK_INFRA_AO_MSDC0 28
#define CLK_INFRA_AO_MSDCFDE 29
#define CLK_INFRA_AO_MSDC1 30
#define CLK_INFRA_AO_DVFSRC 31
#define CLK_INFRA_AO_GCPU 32
#define CLK_INFRA_AO_TRNG 33
#define CLK_INFRA_AO_AUXADC 34
#define CLK_INFRA_AO_CPUM 35
#define CLK_INFRA_AO_CCIF1_AP 36
#define CLK_INFRA_AO_CCIF1_MD 37
#define CLK_INFRA_AO_AUXADC_MD 38
#define CLK_INFRA_AO_AP_DMA 39
#define CLK_INFRA_AO_XIU 40
#define CLK_INFRA_AO_DEVICE_APC 41
#define CLK_INFRA_AO_CCIF_AP 42
#define CLK_INFRA_AO_DEBUGTOP 43
#define CLK_INFRA_AO_AUDIO 44
#define CLK_INFRA_AO_CCIF_MD 45
#define CLK_INFRA_AO_DXCC_SEC_CORE 46
#define CLK_INFRA_AO_DXCC_AO 47
#define CLK_INFRA_AO_IMP_IIC 48
#define CLK_INFRA_AO_DRAMC_F26M 49
#define CLK_INFRA_AO_RG_PWM_FBCLK6 50
#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51
#define CLK_INFRA_AO_DISP_PWM 52
#define CLK_INFRA_AO_CLDMA_BCLK 53
#define CLK_INFRA_AO_AUDIO_26M_BCLK 54
#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55
#define CLK_INFRA_AO_SPI1 56
#define CLK_INFRA_AO_I2C4 57
#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58
#define CLK_INFRA_AO_SPI2 59
#define CLK_INFRA_AO_SPI3 60
#define CLK_INFRA_AO_SSUSB_TOP_REF 61
#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62
#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63
#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64
#define CLK_INFRA_AO_SSPM 65
#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66
#define CLK_INFRA_AO_I2C5 67
#define CLK_INFRA_AO_I2C5_ARBITER 68
#define CLK_INFRA_AO_I2C5_IMM 69
#define CLK_INFRA_AO_I2C1_ARBITER 70
#define CLK_INFRA_AO_I2C1_IMM 71
#define CLK_INFRA_AO_I2C2_ARBITER 72
#define CLK_INFRA_AO_I2C2_IMM 73
#define CLK_INFRA_AO_SPI4 74
#define CLK_INFRA_AO_SPI5 75
#define CLK_INFRA_AO_CQ_DMA 76
#define CLK_INFRA_AO_BIST2FPC 77
#define CLK_INFRA_AO_MSDC0_SELF 78
#define CLK_INFRA_AO_SPINOR 79
#define CLK_INFRA_AO_SSPM_26M_SELF 80
#define CLK_INFRA_AO_SSPM_32K_SELF 81
#define CLK_INFRA_AO_I2C6 82
#define CLK_INFRA_AO_AP_MSDC0 83
#define CLK_INFRA_AO_MD_MSDC0 84
#define CLK_INFRA_AO_MSDC0_SRC 85
#define CLK_INFRA_AO_MSDC1_SRC 86
#define CLK_INFRA_AO_SEJ_F13M 87
#define CLK_INFRA_AO_AES_TOP0_BCLK 88
#define CLK_INFRA_AO_MCU_PM_BCLK 89
#define CLK_INFRA_AO_CCIF2_AP 90
#define CLK_INFRA_AO_CCIF2_MD 91
#define CLK_INFRA_AO_CCIF3_AP 92
#define CLK_INFRA_AO_CCIF3_MD 93
#define CLK_INFRA_AO_FADSP_26M 94
#define CLK_INFRA_AO_FADSP_32K 95
#define CLK_INFRA_AO_CCIF4_AP 96
#define CLK_INFRA_AO_CCIF4_MD 97
#define CLK_INFRA_AO_FADSP 98
#define CLK_INFRA_AO_FLASHIF_133M 99
#define CLK_INFRA_AO_FLASHIF_66M 100
#define CLK_INFRA_AO_NR_CLK 101
/* APMIXEDSYS */
#define CLK_APMIXED_ARMPLL_LL 0
#define CLK_APMIXED_ARMPLL_BL 1
#define CLK_APMIXED_CCIPLL 2
#define CLK_APMIXED_MAINPLL 3
#define CLK_APMIXED_UNIV2PLL 4
#define CLK_APMIXED_MSDCPLL 5
#define CLK_APMIXED_MMPLL 6
#define CLK_APMIXED_NNAPLL 7
#define CLK_APMIXED_NNA2PLL 8
#define CLK_APMIXED_ADSPPLL 9
#define CLK_APMIXED_MFGPLL 10
#define CLK_APMIXED_TVDPLL 11
#define CLK_APMIXED_APLL1 12
#define CLK_APMIXED_APLL2 13
#define CLK_APMIXED_NR_CLK 14
/* IMP_IIC_WRAP */
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8
#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9
#define CLK_IMP_IIC_WRAP_NR_CLK 10
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1
/* MMSYS */
#define CLK_MM_DISP_MUTEX0 0
#define CLK_MM_APB_MM_BUS 1
#define CLK_MM_DISP_OVL0 2
#define CLK_MM_DISP_RDMA0 3
#define CLK_MM_DISP_OVL0_2L 4
#define CLK_MM_DISP_WDMA0 5
#define CLK_MM_DISP_RSZ0 6
#define CLK_MM_DISP_AAL0 7
#define CLK_MM_DISP_CCORR0 8
#define CLK_MM_DISP_COLOR0 9
#define CLK_MM_SMI_INFRA 10
#define CLK_MM_DISP_DSC_WRAP0 11
#define CLK_MM_DISP_GAMMA0 12
#define CLK_MM_DISP_POSTMASK0 13
#define CLK_MM_DISP_DITHER0 14
#define CLK_MM_SMI_COMMON 15
#define CLK_MM_DSI0 16
#define CLK_MM_DISP_FAKE_ENG0 17
#define CLK_MM_DISP_FAKE_ENG1 18
#define CLK_MM_SMI_GALS 19
#define CLK_MM_SMI_IOMMU 20
#define CLK_MM_DISP_RDMA1 21
#define CLK_MM_DISP_DPI 22
#define CLK_MM_DSI0_DSI_CK_DOMAIN 23
#define CLK_MM_DISP_26M 24
#define CLK_MM_NR_CLK 25
/* WPESYS */
#define CLK_WPE_CK_EN 0
#define CLK_WPE_SMI_LARB8_CK_EN 1
#define CLK_WPE_SYS_EVENT_TX_CK_EN 2
#define CLK_WPE_SMI_LARB8_PCLK_EN 3
#define CLK_WPE_NR_CLK 4
/* IMGSYS1 */
#define CLK_IMG1_LARB9_IMG1 0
#define CLK_IMG1_LARB10_IMG1 1
#define CLK_IMG1_DIP 2
#define CLK_IMG1_GALS_IMG1 3
#define CLK_IMG1_NR_CLK 4
/* IMGSYS2 */
#define CLK_IMG2_LARB9_IMG2 0
#define CLK_IMG2_LARB10_IMG2 1
#define CLK_IMG2_MFB 2
#define CLK_IMG2_WPE 3
#define CLK_IMG2_MSS 4
#define CLK_IMG2_GALS_IMG2 5
#define CLK_IMG2_NR_CLK 6
/* VDECSYS */
#define CLK_VDEC_LARB1_CKEN 0
#define CLK_VDEC_LAT_CKEN 1
#define CLK_VDEC_LAT_ACTIVE 2
#define CLK_VDEC_LAT_CKEN_ENG 3
#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4
#define CLK_VDEC_CKEN 5
#define CLK_VDEC_ACTIVE 6
#define CLK_VDEC_CKEN_ENG 7
#define CLK_VDEC_NR_CLK 8
/* VENCSYS */
#define CLK_VENC_CKE0_LARB 0
#define CLK_VENC_CKE1_VENC 1
#define CLK_VENC_CKE2_JPGENC 2
#define CLK_VENC_CKE5_GALS 3
#define CLK_VENC_NR_CLK 4
/* CAMSYS */
#define CLK_CAM_LARB13 0
#define CLK_CAM_DFP_VAD 1
#define CLK_CAM_LARB14 2
#define CLK_CAM 3
#define CLK_CAMTG 4
#define CLK_CAM_SENINF 5
#define CLK_CAMSV1 6
#define CLK_CAMSV2 7
#define CLK_CAMSV3 8
#define CLK_CAM_CCU0 9
#define CLK_CAM_CCU1 10
#define CLK_CAM_MRAW0 11
#define CLK_CAM_FAKE_ENG 12
#define CLK_CAM_CCU_GALS 13
#define CLK_CAM2MM_GALS 14
#define CLK_CAM_NR_CLK 15
/* CAMSYS_RAWA */
#define CLK_CAM_RAWA_LARBX_RAWA 0
#define CLK_CAM_RAWA 1
#define CLK_CAM_RAWA_CAMTG_RAWA 2
#define CLK_CAM_RAWA_NR_CLK 3
/* CAMSYS_RAWB */
#define CLK_CAM_RAWB_LARBX_RAWB 0
#define CLK_CAM_RAWB 1
#define CLK_CAM_RAWB_CAMTG_RAWB 2
#define CLK_CAM_RAWB_NR_CLK 3
/* MDPSYS */
#define CLK_MDP_RDMA0 0
#define CLK_MDP_TDSHP0 1
#define CLK_MDP_IMG_DL_ASYNC0 2
#define CLK_MDP_IMG_DL_ASYNC1 3
#define CLK_MDP_DISP_RDMA 4
#define CLK_MDP_HMS 5
#define CLK_MDP_SMI0 6
#define CLK_MDP_APB_BUS 7
#define CLK_MDP_WROT0 8
#define CLK_MDP_RSZ0 9
#define CLK_MDP_HDR0 10
#define CLK_MDP_MUTEX0 11
#define CLK_MDP_WROT1 12
#define CLK_MDP_RSZ1 13
#define CLK_MDP_FAKE_ENG0 14
#define CLK_MDP_AAL0 15
#define CLK_MDP_DISP_WDMA 16
#define CLK_MDP_COLOR 17
#define CLK_MDP_IMG_DL_ASYNC2 18
#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19
#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20
#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21
#define CLK_MDP_NR_CLK 22
/* IPESYS */
#define CLK_IPE_LARB19 0
#define CLK_IPE_LARB20 1
#define CLK_IPE_SMI_SUBCOM 2
#define CLK_IPE_FD 3
#define CLK_IPE_FE 4
#define CLK_IPE_RSC 5
#define CLK_IPE_DPE 6
#define CLK_IPE_GALS_IPE 7
#define CLK_IPE_NR_CLK 8
#endif /* _DT_BINDINGS_CLK_MT8186_H */

1
include/dt-bindings/clock/qcom,gcc-msm8976.h
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@ -224,6 +224,7 @@
#define RST_CAMSS_CSI_VFE1_BCR 7
#define RST_CAMSS_VFE1_BCR 8
#define RST_CAMSS_CPP_BCR 9
#define RST_MSS_BCR 10
/* GDSCs */
#define VENUS_GDSC 0

4
include/dt-bindings/clock/qcom,gcc-msm8998.h
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@ -186,6 +186,10 @@
#define UFS_UNIPRO_CORE_CLK_SRC 177
#define GCC_MMSS_GPLL0_CLK 178
#define HMSS_GPLL0_CLK_SRC 179
#define GCC_IM_SLEEP 180
#define AGGRE2_SNOC_NORTH_AXI 181
#define SSC_XO 182
#define SSC_CNOC_AHBS_CLK 183
#define PCIE_0_GDSC 0
#define UFS_GDSC 1

496
include/dt-bindings/clock/qcom,gcc-sc8280xp.h Normal file
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@ -0,0 +1,496 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Ltd.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL2 2
#define GCC_GPLL4 3
#define GCC_GPLL7 4
#define GCC_GPLL8 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7
#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8
#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9
#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10
#define GCC_AGGRE_UFS_CARD_AXI_CLK 11
#define GCC_AGGRE_UFS_PHY_AXI_CLK 12
#define GCC_AGGRE_USB3_MP_AXI_CLK 13
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14
#define GCC_AGGRE_USB3_SEC_AXI_CLK 15
#define GCC_AGGRE_USB4_1_AXI_CLK 16
#define GCC_AGGRE_USB4_AXI_CLK 17
#define GCC_AGGRE_USB_NOC_AXI_CLK 18
#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19
#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20
#define GCC_AHB2PHY0_CLK 21
#define GCC_AHB2PHY2_CLK 22
#define GCC_BOOT_ROM_AHB_CLK 23
#define GCC_CAMERA_AHB_CLK 24
#define GCC_CAMERA_HF_AXI_CLK 25
#define GCC_CAMERA_SF_AXI_CLK 26
#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27
#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28
#define GCC_CAMERA_THROTTLE_XO_CLK 29
#define GCC_CAMERA_XO_CLK 30
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33
#define GCC_CNOC_PCIE0_TUNNEL_CLK 34
#define GCC_CNOC_PCIE1_TUNNEL_CLK 35
#define GCC_CNOC_PCIE4_QX_CLK 36
#define GCC_DDRSS_GPU_AXI_CLK 37
#define GCC_DDRSS_PCIE_SF_TBU_CLK 38
#define GCC_DISP1_AHB_CLK 39
#define GCC_DISP1_HF_AXI_CLK 40
#define GCC_DISP1_SF_AXI_CLK 41
#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42
#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43
#define GCC_DISP1_XO_CLK 44
#define GCC_DISP_AHB_CLK 45
#define GCC_DISP_HF_AXI_CLK 46
#define GCC_DISP_SF_AXI_CLK 47
#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48
#define GCC_DISP_THROTTLE_RT_AXI_CLK 49
#define GCC_DISP_XO_CLK 50
#define GCC_EMAC0_AXI_CLK 51
#define GCC_EMAC0_PTP_CLK 52
#define GCC_EMAC0_PTP_CLK_SRC 53
#define GCC_EMAC0_RGMII_CLK 54
#define GCC_EMAC0_RGMII_CLK_SRC 55
#define GCC_EMAC0_SLV_AHB_CLK 56
#define GCC_EMAC1_AXI_CLK 57
#define GCC_EMAC1_PTP_CLK 58
#define GCC_EMAC1_PTP_CLK_SRC 59
#define GCC_EMAC1_RGMII_CLK 60
#define GCC_EMAC1_RGMII_CLK_SRC 61
#define GCC_EMAC1_SLV_AHB_CLK 62
#define GCC_GP1_CLK 63
#define GCC_GP1_CLK_SRC 64
#define GCC_GP2_CLK 65
#define GCC_GP2_CLK_SRC 66
#define GCC_GP3_CLK 67
#define GCC_GP3_CLK_SRC 68
#define GCC_GP4_CLK 69
#define GCC_GP4_CLK_SRC 70
#define GCC_GP5_CLK 71
#define GCC_GP5_CLK_SRC 72
#define GCC_GPU_CFG_AHB_CLK 73
#define GCC_GPU_GPLL0_CLK_SRC 74
#define GCC_GPU_GPLL0_DIV_CLK_SRC 75
#define GCC_GPU_IREF_EN 76
#define GCC_GPU_MEMNOC_GFX_CLK 77
#define GCC_GPU_SNOC_DVM_GFX_CLK 78
#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79
#define GCC_GPU_TCU_THROTTLE_CLK 80
#define GCC_PCIE0_PHY_RCHNG_CLK 81
#define GCC_PCIE1_PHY_RCHNG_CLK 82
#define GCC_PCIE2A_PHY_RCHNG_CLK 83
#define GCC_PCIE2B_PHY_RCHNG_CLK 84
#define GCC_PCIE3A_PHY_RCHNG_CLK 85
#define GCC_PCIE3B_PHY_RCHNG_CLK 86
#define GCC_PCIE4_PHY_RCHNG_CLK 87
#define GCC_PCIE_0_AUX_CLK 88
#define GCC_PCIE_0_AUX_CLK_SRC 89
#define GCC_PCIE_0_CFG_AHB_CLK 90
#define GCC_PCIE_0_MSTR_AXI_CLK 91
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92
#define GCC_PCIE_0_PIPE_CLK 93
#define GCC_PCIE_0_SLV_AXI_CLK 94
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95
#define GCC_PCIE_1_AUX_CLK 96
#define GCC_PCIE_1_AUX_CLK_SRC 97
#define GCC_PCIE_1_CFG_AHB_CLK 98
#define GCC_PCIE_1_MSTR_AXI_CLK 99
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100
#define GCC_PCIE_1_PIPE_CLK 101
#define GCC_PCIE_1_SLV_AXI_CLK 102
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103
#define GCC_PCIE_2A2B_CLKREF_CLK 104
#define GCC_PCIE_2A_AUX_CLK 105
#define GCC_PCIE_2A_AUX_CLK_SRC 106
#define GCC_PCIE_2A_CFG_AHB_CLK 107
#define GCC_PCIE_2A_MSTR_AXI_CLK 108
#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109
#define GCC_PCIE_2A_PIPE_CLK 110
#define GCC_PCIE_2A_PIPE_CLK_SRC 111
#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112
#define GCC_PCIE_2A_PIPEDIV2_CLK 113
#define GCC_PCIE_2A_SLV_AXI_CLK 114
#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115
#define GCC_PCIE_2B_AUX_CLK 116
#define GCC_PCIE_2B_AUX_CLK_SRC 117
#define GCC_PCIE_2B_CFG_AHB_CLK 118
#define GCC_PCIE_2B_MSTR_AXI_CLK 119
#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120
#define GCC_PCIE_2B_PIPE_CLK 121
#define GCC_PCIE_2B_PIPE_CLK_SRC 122
#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123
#define GCC_PCIE_2B_PIPEDIV2_CLK 124
#define GCC_PCIE_2B_SLV_AXI_CLK 125
#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126
#define GCC_PCIE_3A3B_CLKREF_CLK 127
#define GCC_PCIE_3A_AUX_CLK 128
#define GCC_PCIE_3A_AUX_CLK_SRC 129
#define GCC_PCIE_3A_CFG_AHB_CLK 130
#define GCC_PCIE_3A_MSTR_AXI_CLK 131
#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132
#define GCC_PCIE_3A_PIPE_CLK 133
#define GCC_PCIE_3A_PIPE_CLK_SRC 134
#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135
#define GCC_PCIE_3A_PIPEDIV2_CLK 136
#define GCC_PCIE_3A_SLV_AXI_CLK 137
#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138
#define GCC_PCIE_3B_AUX_CLK 139
#define GCC_PCIE_3B_AUX_CLK_SRC 140
#define GCC_PCIE_3B_CFG_AHB_CLK 141
#define GCC_PCIE_3B_MSTR_AXI_CLK 142
#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143
#define GCC_PCIE_3B_PIPE_CLK 144
#define GCC_PCIE_3B_PIPE_CLK_SRC 145
#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146
#define GCC_PCIE_3B_PIPEDIV2_CLK 147
#define GCC_PCIE_3B_SLV_AXI_CLK 148
#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149
#define GCC_PCIE_4_AUX_CLK 150
#define GCC_PCIE_4_AUX_CLK_SRC 151
#define GCC_PCIE_4_CFG_AHB_CLK 152
#define GCC_PCIE_4_CLKREF_CLK 153
#define GCC_PCIE_4_MSTR_AXI_CLK 154
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155
#define GCC_PCIE_4_PIPE_CLK 156
#define GCC_PCIE_4_PIPE_CLK_SRC 157
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158
#define GCC_PCIE_4_PIPEDIV2_CLK 159
#define GCC_PCIE_4_SLV_AXI_CLK 160
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161
#define GCC_PCIE_RSCC_AHB_CLK 162
#define GCC_PCIE_RSCC_XO_CLK 163
#define GCC_PCIE_RSCC_XO_CLK_SRC 164
#define GCC_PCIE_THROTTLE_CFG_CLK 165
#define GCC_PDM2_CLK 166
#define GCC_PDM2_CLK_SRC 167
#define GCC_PDM_AHB_CLK 168
#define GCC_PDM_XO4_CLK 169
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170
#define GCC_QMIP_CAMERA_RT_AHB_CLK 171
#define GCC_QMIP_DISP1_AHB_CLK 172
#define GCC_QMIP_DISP1_ROT_AHB_CLK 173
#define GCC_QMIP_DISP_AHB_CLK 174
#define GCC_QMIP_DISP_ROT_AHB_CLK 175
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178
#define GCC_QUPV3_WRAP0_CORE_CLK 179
#define GCC_QUPV3_WRAP0_QSPI0_CLK 180
#define GCC_QUPV3_WRAP0_S0_CLK 181
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182
#define GCC_QUPV3_WRAP0_S1_CLK 183
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184
#define GCC_QUPV3_WRAP0_S2_CLK 185
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186
#define GCC_QUPV3_WRAP0_S3_CLK 187
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188
#define GCC_QUPV3_WRAP0_S4_CLK 189
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190
#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191
#define GCC_QUPV3_WRAP0_S5_CLK 192
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193
#define GCC_QUPV3_WRAP0_S6_CLK 194
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195
#define GCC_QUPV3_WRAP0_S7_CLK 196
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198
#define GCC_QUPV3_WRAP1_CORE_CLK 199
#define GCC_QUPV3_WRAP1_QSPI0_CLK 200
#define GCC_QUPV3_WRAP1_S0_CLK 201
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202
#define GCC_QUPV3_WRAP1_S1_CLK 203
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204
#define GCC_QUPV3_WRAP1_S2_CLK 205
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206
#define GCC_QUPV3_WRAP1_S3_CLK 207
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208
#define GCC_QUPV3_WRAP1_S4_CLK 209
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210
#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211
#define GCC_QUPV3_WRAP1_S5_CLK 212
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213
#define GCC_QUPV3_WRAP1_S6_CLK 214
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215
#define GCC_QUPV3_WRAP1_S7_CLK 216
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218
#define GCC_QUPV3_WRAP2_CORE_CLK 219
#define GCC_QUPV3_WRAP2_QSPI0_CLK 220
#define GCC_QUPV3_WRAP2_S0_CLK 221
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222
#define GCC_QUPV3_WRAP2_S1_CLK 223
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224
#define GCC_QUPV3_WRAP2_S2_CLK 225
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226
#define GCC_QUPV3_WRAP2_S3_CLK 227
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228
#define GCC_QUPV3_WRAP2_S4_CLK 229
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230
#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231
#define GCC_QUPV3_WRAP2_S5_CLK 232
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233
#define GCC_QUPV3_WRAP2_S6_CLK 234
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235
#define GCC_QUPV3_WRAP2_S7_CLK 236
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243
#define GCC_SDCC2_AHB_CLK 244
#define GCC_SDCC2_APPS_CLK 245
#define GCC_SDCC2_APPS_CLK_SRC 246
#define GCC_SDCC4_AHB_CLK 247
#define GCC_SDCC4_APPS_CLK 248
#define GCC_SDCC4_APPS_CLK_SRC 249
#define GCC_SYS_NOC_USB_AXI_CLK 250
#define GCC_UFS_1_CARD_CLKREF_CLK 251
#define GCC_UFS_CARD_AHB_CLK 252
#define GCC_UFS_CARD_AXI_CLK 253
#define GCC_UFS_CARD_AXI_CLK_SRC 254
#define GCC_UFS_CARD_CLKREF_CLK 255
#define GCC_UFS_CARD_ICE_CORE_CLK 256
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257
#define GCC_UFS_CARD_PHY_AUX_CLK 258
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267
#define GCC_UFS_PHY_AHB_CLK 268
#define GCC_UFS_PHY_AXI_CLK 269
#define GCC_UFS_PHY_AXI_CLK_SRC 270
#define GCC_UFS_PHY_ICE_CORE_CLK 271
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272
#define GCC_UFS_PHY_PHY_AUX_CLK 273
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282
#define GCC_UFS_REF_CLKREF_CLK 283
#define GCC_USB2_HS0_CLKREF_CLK 284
#define GCC_USB2_HS1_CLKREF_CLK 285
#define GCC_USB2_HS2_CLKREF_CLK 286
#define GCC_USB2_HS3_CLKREF_CLK 287
#define GCC_USB30_MP_MASTER_CLK 288
#define GCC_USB30_MP_MASTER_CLK_SRC 289
#define GCC_USB30_MP_MOCK_UTMI_CLK 290
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292
#define GCC_USB30_MP_SLEEP_CLK 293
#define GCC_USB30_PRIM_MASTER_CLK 294
#define GCC_USB30_PRIM_MASTER_CLK_SRC 295
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298
#define GCC_USB30_PRIM_SLEEP_CLK 299
#define GCC_USB30_SEC_MASTER_CLK 300
#define GCC_USB30_SEC_MASTER_CLK_SRC 301
#define GCC_USB30_SEC_MOCK_UTMI_CLK 302
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304
#define GCC_USB30_SEC_SLEEP_CLK 305
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307
#define GCC_USB3_MP0_CLKREF_CLK 308
#define GCC_USB3_MP1_CLKREF_CLK 309
#define GCC_USB3_MP_PHY_AUX_CLK 310
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311
#define GCC_USB3_MP_PHY_COM_AUX_CLK 312
#define GCC_USB3_MP_PHY_PIPE_0_CLK 313
#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314
#define GCC_USB3_MP_PHY_PIPE_1_CLK 315
#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316
#define GCC_USB3_PRIM_PHY_AUX_CLK 317
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319
#define GCC_USB3_PRIM_PHY_PIPE_CLK 320
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321
#define GCC_USB3_SEC_PHY_AUX_CLK 322
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324
#define GCC_USB3_SEC_PHY_PIPE_CLK 325
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326
#define GCC_USB4_1_CFG_AHB_CLK 327
#define GCC_USB4_1_DP_CLK 328
#define GCC_USB4_1_MASTER_CLK 329
#define GCC_USB4_1_MASTER_CLK_SRC 330
#define GCC_USB4_1_PHY_DP_CLK_SRC 331
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336
#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337
#define GCC_USB4_1_PHY_RX0_CLK 338
#define GCC_USB4_1_PHY_RX0_CLK_SRC 339
#define GCC_USB4_1_PHY_RX1_CLK 340
#define GCC_USB4_1_PHY_RX1_CLK_SRC 341
#define GCC_USB4_1_PHY_SYS_CLK_SRC 342
#define GCC_USB4_1_PHY_USB_PIPE_CLK 343
#define GCC_USB4_1_SB_IF_CLK 344
#define GCC_USB4_1_SB_IF_CLK_SRC 345
#define GCC_USB4_1_SYS_CLK 346
#define GCC_USB4_1_TMU_CLK 347
#define GCC_USB4_1_TMU_CLK_SRC 348
#define GCC_USB4_CFG_AHB_CLK 349
#define GCC_USB4_CLKREF_CLK 350
#define GCC_USB4_DP_CLK 351
#define GCC_USB4_EUD_CLKREF_CLK 352
#define GCC_USB4_MASTER_CLK 353
#define GCC_USB4_MASTER_CLK_SRC 354
#define GCC_USB4_PHY_DP_CLK_SRC 355
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357
#define GCC_USB4_PHY_PCIE_PIPE_CLK 358
#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359
#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360
#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361
#define GCC_USB4_PHY_RX0_CLK 362
#define GCC_USB4_PHY_RX0_CLK_SRC 363
#define GCC_USB4_PHY_RX1_CLK 364
#define GCC_USB4_PHY_RX1_CLK_SRC 365
#define GCC_USB4_PHY_SYS_CLK_SRC 366
#define GCC_USB4_PHY_USB_PIPE_CLK 367
#define GCC_USB4_SB_IF_CLK 368
#define GCC_USB4_SB_IF_CLK_SRC 369
#define GCC_USB4_SYS_CLK 370
#define GCC_USB4_TMU_CLK 371
#define GCC_USB4_TMU_CLK_SRC 372
#define GCC_VIDEO_AHB_CLK 373
#define GCC_VIDEO_AXI0_CLK 374
#define GCC_VIDEO_AXI1_CLK 375
#define GCC_VIDEO_CVP_THROTTLE_CLK 376
#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377
#define GCC_VIDEO_XO_CLK 378
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388
/* GCC resets */
#define GCC_EMAC0_BCR 0
#define GCC_EMAC1_BCR 1
#define GCC_PCIE_0_LINK_DOWN_BCR 2
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3
#define GCC_PCIE_0_PHY_BCR 4
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_TUNNEL_BCR 6
#define GCC_PCIE_1_LINK_DOWN_BCR 7
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_1_PHY_BCR 9
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_TUNNEL_BCR 11
#define GCC_PCIE_2A_BCR 12
#define GCC_PCIE_2A_LINK_DOWN_BCR 13
#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14
#define GCC_PCIE_2A_PHY_BCR 15
#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16
#define GCC_PCIE_2B_BCR 17
#define GCC_PCIE_2B_LINK_DOWN_BCR 18
#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19
#define GCC_PCIE_2B_PHY_BCR 20
#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21
#define GCC_PCIE_3A_BCR 22
#define GCC_PCIE_3A_LINK_DOWN_BCR 23
#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24
#define GCC_PCIE_3A_PHY_BCR 25
#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26
#define GCC_PCIE_3B_BCR 27
#define GCC_PCIE_3B_LINK_DOWN_BCR 28
#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29
#define GCC_PCIE_3B_PHY_BCR 30
#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31
#define GCC_PCIE_4_BCR 32
#define GCC_PCIE_4_LINK_DOWN_BCR 33
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34
#define GCC_PCIE_4_PHY_BCR 35
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36
#define GCC_PCIE_PHY_CFG_AHB_BCR 37
#define GCC_PCIE_PHY_COM_BCR 38
#define GCC_PCIE_RSCC_BCR 39
#define GCC_QUSB2PHY_HS0_MP_BCR 40
#define GCC_QUSB2PHY_HS1_MP_BCR 41
#define GCC_QUSB2PHY_HS2_MP_BCR 42
#define GCC_QUSB2PHY_HS3_MP_BCR 43
#define GCC_QUSB2PHY_PRIM_BCR 44
#define GCC_QUSB2PHY_SEC_BCR 45
#define GCC_SDCC2_BCR 46
#define GCC_SDCC4_BCR 47
#define GCC_UFS_CARD_BCR 48
#define GCC_UFS_PHY_BCR 49
#define GCC_USB2_PHY_PRIM_BCR 50
#define GCC_USB2_PHY_SEC_BCR 51
#define GCC_USB30_MP_BCR 52
#define GCC_USB30_PRIM_BCR 53
#define GCC_USB30_SEC_BCR 54
#define GCC_USB3_DP_PHY_PRIM_BCR 55
#define GCC_USB3_DP_PHY_SEC_BCR 56
#define GCC_USB3_PHY_PRIM_BCR 57
#define GCC_USB3_PHY_SEC_BCR 58
#define GCC_USB3_UNIPHY_MP0_BCR 59
#define GCC_USB3_UNIPHY_MP1_BCR 60
#define GCC_USB3PHY_PHY_PRIM_BCR 61
#define GCC_USB3PHY_PHY_SEC_BCR 62
#define GCC_USB3UNIPHY_PHY_MP0_BCR 63
#define GCC_USB3UNIPHY_PHY_MP1_BCR 64
#define GCC_USB4_1_BCR 65
#define GCC_USB4_1_DP_PHY_PRIM_BCR 66
#define GCC_USB4_1_DPPHY_AUX_BCR 67
#define GCC_USB4_1_PHY_PRIM_BCR 68
#define GCC_USB4_BCR 69
#define GCC_USB4_DP_PHY_PRIM_BCR 70
#define GCC_USB4_DPPHY_AUX_BCR 71
#define GCC_USB4_PHY_PRIM_BCR 72
#define GCC_USB4PHY_1_PHY_PRIM_BCR 73
#define GCC_USB4PHY_PHY_PRIM_BCR 74
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75
#define GCC_VIDEO_BCR 76
#define GCC_VIDEO_AXI0_CLK_ARES 77
#define GCC_VIDEO_AXI1_CLK_ARES 78
/* GCC GDSCs */
#define PCIE_0_TUNNEL_GDSC 0
#define PCIE_1_TUNNEL_GDSC 1
#define PCIE_2A_GDSC 2
#define PCIE_2B_GDSC 3
#define PCIE_3A_GDSC 4
#define PCIE_3B_GDSC 5
#define PCIE_4_GDSC 6
#define UFS_CARD_GDSC 7
#define UFS_PHY_GDSC 8
#define USB30_MP_GDSC 9
#define USB30_PRIM_GDSC 10
#define USB30_SEC_GDSC 11
#endif

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include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
/* LPASS_AUDIO_CC clocks */
#define LPASS_AUDIO_CC_PLL 0
#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1
#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
#define LPASS_AON_CC_PLL_OUT_ODD 3
#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
#define LPASS_AON_CC_TX_MCLK_CLK 8
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
#define LPASS_AON_CC_VA_MEM0_CLK 10
/* LPASS_AON_CC power domains */
#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
/* LPASS_CORE_CC clocks */
#define LPASS_CORE_CC_DIG_PLL 0
#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1
#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2
#define LPASS_CORE_CC_CORE_CLK 3
#define LPASS_CORE_CC_CORE_CLK_SRC 4
#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5
#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6
#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7
#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8
#define LPASS_CORE_CC_LPM_CORE_CLK 9
#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
/* LPASS_CORE_CC power domains */
#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0
#endif

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include/dt-bindings/clock/r8a779g0-cpg-mssr.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_ZX 0
#define R8A779G0_CLK_ZS 1
#define R8A779G0_CLK_ZT 2
#define R8A779G0_CLK_ZTR 3
#define R8A779G0_CLK_S0D2 4
#define R8A779G0_CLK_S0D3 5
#define R8A779G0_CLK_S0D4 6
#define R8A779G0_CLK_S0D1_VIO 7
#define R8A779G0_CLK_S0D2_VIO 8
#define R8A779G0_CLK_S0D4_VIO 9
#define R8A779G0_CLK_S0D8_VIO 10
#define R8A779G0_CLK_S0D1_VC 11
#define R8A779G0_CLK_S0D2_VC 12
#define R8A779G0_CLK_S0D4_VC 13
#define R8A779G0_CLK_S0D2_MM 14
#define R8A779G0_CLK_S0D4_MM 15
#define R8A779G0_CLK_S0D2_U3DG 16
#define R8A779G0_CLK_S0D4_U3DG 17
#define R8A779G0_CLK_S0D2_RT 18
#define R8A779G0_CLK_S0D3_RT 19
#define R8A779G0_CLK_S0D4_RT 20
#define R8A779G0_CLK_S0D6_RT 21
#define R8A779G0_CLK_S0D24_RT 22
#define R8A779G0_CLK_S0D2_PER 23
#define R8A779G0_CLK_S0D3_PER 24
#define R8A779G0_CLK_S0D4_PER 25
#define R8A779G0_CLK_S0D6_PER 26
#define R8A779G0_CLK_S0D12_PER 27
#define R8A779G0_CLK_S0D24_PER 28
#define R8A779G0_CLK_S0D1_HSC 29
#define R8A779G0_CLK_S0D2_HSC 30
#define R8A779G0_CLK_S0D4_HSC 31
#define R8A779G0_CLK_S0D2_CC 32
#define R8A779G0_CLK_SVD1_IR 33
#define R8A779G0_CLK_SVD2_IR 34
#define R8A779G0_CLK_SVD1_VIP 35
#define R8A779G0_CLK_SVD2_VIP 36
#define R8A779G0_CLK_CL 37
#define R8A779G0_CLK_CL16M 38
#define R8A779G0_CLK_CL16M_MM 39
#define R8A779G0_CLK_CL16M_RT 40
#define R8A779G0_CLK_CL16M_PER 41
#define R8A779G0_CLK_CL16M_HSC 42
#define R8A779G0_CLK_Z0 43
#define R8A779G0_CLK_ZB3 44
#define R8A779G0_CLK_ZB3D2 45
#define R8A779G0_CLK_ZB3D4 46
#define R8A779G0_CLK_ZG 47
#define R8A779G0_CLK_SD0H 48
#define R8A779G0_CLK_SD0 49
#define R8A779G0_CLK_RPC 50
#define R8A779G0_CLK_RPCD2 51
#define R8A779G0_CLK_MSO 52
#define R8A779G0_CLK_CANFD 53
#define R8A779G0_CLK_CSI 54
#define R8A779G0_CLK_FRAY 55
#define R8A779G0_CLK_IPC 56
#define R8A779G0_CLK_SASYNCRT 57
#define R8A779G0_CLK_SASYNCPERD1 58
#define R8A779G0_CLK_SASYNCPERD2 59
#define R8A779G0_CLK_SASYNCPERD4 60
#define R8A779G0_CLK_VIOBUS 61
#define R8A779G0_CLK_VIOBUSD2 62
#define R8A779G0_CLK_VCBUS 63
#define R8A779G0_CLK_VCBUSD2 64
#define R8A779G0_CLK_DSIEXT 65
#define R8A779G0_CLK_DSIREF 66
#define R8A779G0_CLK_ADGH 67
#define R8A779G0_CLK_OSC 68
#define R8A779G0_CLK_ZR0 69
#define R8A779G0_CLK_ZR1 70
#define R8A779G0_CLK_ZR2 71
#define R8A779G0_CLK_IMPA 72
#define R8A779G0_CLK_IMPAD4 73
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G043 CPG Core Clocks */
#define R9A07G043_CLK_I 0
#define R9A07G043_CLK_I2 1
#define R9A07G043_CLK_S0 2
#define R9A07G043_CLK_SPI0 3
#define R9A07G043_CLK_SPI1 4
#define R9A07G043_CLK_SD0 5
#define R9A07G043_CLK_SD1 6
#define R9A07G043_CLK_M0 7
#define R9A07G043_CLK_M2 8
#define R9A07G043_CLK_M3 9
#define R9A07G043_CLK_HP 10
#define R9A07G043_CLK_TSU 11
#define R9A07G043_CLK_ZT 12
#define R9A07G043_CLK_P0 13
#define R9A07G043_CLK_P1 14
#define R9A07G043_CLK_P2 15
#define R9A07G043_CLK_AT 16
#define R9A07G043_OSCCLK 17
#define R9A07G043_CLK_P0_DIV2 18
/* R9A07G043 Module Clocks */
#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */
#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */
#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */
#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */
#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */
#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */
#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */
#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */
#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */
#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */
#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */
#define R9A07G043_SYC_CNT_CLK 11
#define R9A07G043_DMAC_ACLK 12
#define R9A07G043_DMAC_PCLK 13
#define R9A07G043_OSTM0_PCLK 14
#define R9A07G043_OSTM1_PCLK 15
#define R9A07G043_OSTM2_PCLK 16
#define R9A07G043_MTU_X_MCK_MTU3 17
#define R9A07G043_POE3_CLKM_POE 18
#define R9A07G043_WDT0_PCLK 19
#define R9A07G043_WDT0_CLK 20
#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */
#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */
#define R9A07G043_SPI_CLK2 23
#define R9A07G043_SPI_CLK 24
#define R9A07G043_SDHI0_IMCLK 25
#define R9A07G043_SDHI0_IMCLK2 26
#define R9A07G043_SDHI0_CLK_HS 27
#define R9A07G043_SDHI0_ACLK 28
#define R9A07G043_SDHI1_IMCLK 29
#define R9A07G043_SDHI1_IMCLK2 30
#define R9A07G043_SDHI1_CLK_HS 31
#define R9A07G043_SDHI1_ACLK 32
#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */
#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */
#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */
#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */
#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */
#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */
#define R9A07G043_SSI0_PCLK2 42
#define R9A07G043_SSI0_PCLK_SFR 43
#define R9A07G043_SSI1_PCLK2 44
#define R9A07G043_SSI1_PCLK_SFR 45
#define R9A07G043_SSI2_PCLK2 46
#define R9A07G043_SSI2_PCLK_SFR 47
#define R9A07G043_SSI3_PCLK2 48
#define R9A07G043_SSI3_PCLK_SFR 49
#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */
#define R9A07G043_USB_U2H0_HCLK 51
#define R9A07G043_USB_U2H1_HCLK 52
#define R9A07G043_USB_U2P_EXR_CPUCLK 53
#define R9A07G043_USB_PCLK 54
#define R9A07G043_ETH0_CLK_AXI 55
#define R9A07G043_ETH0_CLK_CHI 56
#define R9A07G043_ETH1_CLK_AXI 57
#define R9A07G043_ETH1_CLK_CHI 58
#define R9A07G043_I2C0_PCLK 59
#define R9A07G043_I2C1_PCLK 60
#define R9A07G043_I2C2_PCLK 61
#define R9A07G043_I2C3_PCLK 62
#define R9A07G043_SCIF0_CLK_PCK 63
#define R9A07G043_SCIF1_CLK_PCK 64
#define R9A07G043_SCIF2_CLK_PCK 65
#define R9A07G043_SCIF3_CLK_PCK 66
#define R9A07G043_SCIF4_CLK_PCK 67
#define R9A07G043_SCI0_CLKP 68
#define R9A07G043_SCI1_CLKP 69
#define R9A07G043_IRDA_CLKP 70
#define R9A07G043_RSPI0_CLKB 71
#define R9A07G043_RSPI1_CLKB 72
#define R9A07G043_RSPI2_CLKB 73
#define R9A07G043_CANFD_PCLK 74
#define R9A07G043_GPIO_HCLK 75
#define R9A07G043_ADC_ADCLK 76
#define R9A07G043_ADC_PCLK 77
#define R9A07G043_TSU_PCLK 78
/* R9A07G043 Resets */
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */
#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */
#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */
#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */
#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */
#define R9A07G043_DMAC_ARESETN 17
#define R9A07G043_DMAC_RST_ASYNC 18
#define R9A07G043_SYC_RESETN 19
#define R9A07G043_OSTM0_PRESETZ 20
#define R9A07G043_OSTM1_PRESETZ 21
#define R9A07G043_OSTM2_PRESETZ 22
#define R9A07G043_MTU_X_PRESET_MTU3 23
#define R9A07G043_POE3_RST_M_REG 24
#define R9A07G043_WDT0_PRESETN 25
#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */
#define R9A07G043_SPI_RST 27
#define R9A07G043_SDHI0_IXRST 28
#define R9A07G043_SDHI1_IXRST 29
#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */
#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */
#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */
#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */
#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */
#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */
#define R9A07G043_SSI0_RST_M2_REG 36
#define R9A07G043_SSI1_RST_M2_REG 37
#define R9A07G043_SSI2_RST_M2_REG 38
#define R9A07G043_SSI3_RST_M2_REG 39
#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */
#define R9A07G043_USB_U2H0_HRESETN 41
#define R9A07G043_USB_U2H1_HRESETN 42
#define R9A07G043_USB_U2P_EXL_SYSRST 43
#define R9A07G043_USB_PRESETN 44
#define R9A07G043_ETH0_RST_HW_N 45
#define R9A07G043_ETH1_RST_HW_N 46
#define R9A07G043_I2C0_MRST 47
#define R9A07G043_I2C1_MRST 48
#define R9A07G043_I2C2_MRST 49
#define R9A07G043_I2C3_MRST 50
#define R9A07G043_SCIF0_RST_SYSTEM_N 51
#define R9A07G043_SCIF1_RST_SYSTEM_N 52
#define R9A07G043_SCIF2_RST_SYSTEM_N 53
#define R9A07G043_SCIF3_RST_SYSTEM_N 54
#define R9A07G043_SCIF4_RST_SYSTEM_N 55
#define R9A07G043_SCI0_RST 56
#define R9A07G043_SCI1_RST 57
#define R9A07G043_IRDA_RST 58
#define R9A07G043_RSPI0_RST 59
#define R9A07G043_RSPI1_RST 60
#define R9A07G043_RSPI2_RST 61
#define R9A07G043_CANFD_RSTP_N 62
#define R9A07G043_CANFD_RSTC_N 63
#define R9A07G043_GPIO_RSTN 64
#define R9A07G043_GPIO_PORT_RESETN 65
#define R9A07G043_GPIO_SPARE_RESETN 66
#define R9A07G043_ADC_PRESETN 67
#define R9A07G043_ADC_ADRST_N 68
#define R9A07G043_TSU_PRESETN 69
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Module Clocks */
#define R9A09G011_SYS_CLK 0
#define R9A09G011_PFC_PCLK 1
#define R9A09G011_PMC_CORE_CLOCK 2
#define R9A09G011_GIC_CLK 3
#define R9A09G011_RAMA_ACLK 4
#define R9A09G011_ROMA_ACLK 5
#define R9A09G011_SEC_ACLK 6
#define R9A09G011_SEC_PCLK 7
#define R9A09G011_SEC_TCLK 8
#define R9A09G011_DMAA_ACLK 9
#define R9A09G011_TSU0_PCLK 10
#define R9A09G011_TSU1_PCLK 11
#define R9A09G011_CST_TRACECLK 12
#define R9A09G011_CST_SB_CLK 13
#define R9A09G011_CST_AHB_CLK 14
#define R9A09G011_CST_ATB_SB_CLK 15
#define R9A09G011_CST_TS_SB_CLK 16
#define R9A09G011_SDI0_ACLK 17
#define R9A09G011_SDI0_IMCLK 18
#define R9A09G011_SDI0_IMCLK2 19
#define R9A09G011_SDI0_CLK_HS 20
#define R9A09G011_SDI1_ACLK 21
#define R9A09G011_SDI1_IMCLK 22
#define R9A09G011_SDI1_IMCLK2 23
#define R9A09G011_SDI1_CLK_HS 24
#define R9A09G011_EMM_ACLK 25
#define R9A09G011_EMM_IMCLK 26
#define R9A09G011_EMM_IMCLK2 27
#define R9A09G011_EMM_CLK_HS 28
#define R9A09G011_NFI_ACLK 29
#define R9A09G011_NFI_NF_CLK 30
#define R9A09G011_PCI_ACLK 31
#define R9A09G011_PCI_CLK_PMU 32
#define R9A09G011_PCI_APB_CLK 33
#define R9A09G011_USB_ACLK_H 34
#define R9A09G011_USB_ACLK_P 35
#define R9A09G011_USB_PCLK 36
#define R9A09G011_ETH0_CLK_AXI 37
#define R9A09G011_ETH0_CLK_CHI 38
#define R9A09G011_ETH0_GPTP_EXT 39
#define R9A09G011_SDT_CLK 40
#define R9A09G011_SDT_CLKAPB 41
#define R9A09G011_SDT_CLK48 42
#define R9A09G011_GRP_CLK 43
#define R9A09G011_CIF_P0_CLK 44
#define R9A09G011_CIF_P1_CLK 45
#define R9A09G011_CIF_APB_CLK 46
#define R9A09G011_DCI_CLKAXI 47
#define R9A09G011_DCI_CLKAPB 48
#define R9A09G011_DCI_CLKDCI2 49
#define R9A09G011_HMI_PCLK 50
#define R9A09G011_LCI_PCLK 51
#define R9A09G011_LCI_ACLK 52
#define R9A09G011_LCI_VCLK 53
#define R9A09G011_LCI_LPCLK 54
#define R9A09G011_AUI_CLK 55
#define R9A09G011_AUI_CLKAXI 56
#define R9A09G011_AUI_CLKAPB 57
#define R9A09G011_AUMCLK 58
#define R9A09G011_GMCLK0 59
#define R9A09G011_GMCLK1 60
#define R9A09G011_MTR_CLK0 61
#define R9A09G011_MTR_CLK1 62
#define R9A09G011_MTR_CLKAPB 63
#define R9A09G011_GFT_CLK 64
#define R9A09G011_GFT_CLKAPB 65
#define R9A09G011_GFT_MCLK 66
#define R9A09G011_ATGA_CLK 67
#define R9A09G011_ATGA_CLKAPB 68
#define R9A09G011_ATGB_CLK 69
#define R9A09G011_ATGB_CLKAPB 70
#define R9A09G011_SYC_CNT_CLK 71
#define R9A09G011_CPERI_GRPA_PCLK 72
#define R9A09G011_TIM0_CLK 73
#define R9A09G011_TIM1_CLK 74
#define R9A09G011_TIM2_CLK 75
#define R9A09G011_TIM3_CLK 76
#define R9A09G011_TIM4_CLK 77
#define R9A09G011_TIM5_CLK 78
#define R9A09G011_TIM6_CLK 79
#define R9A09G011_TIM7_CLK 80
#define R9A09G011_IIC_PCLK0 81
#define R9A09G011_CPERI_GRPB_PCLK 82
#define R9A09G011_TIM8_CLK 83
#define R9A09G011_TIM9_CLK 84
#define R9A09G011_TIM10_CLK 85
#define R9A09G011_TIM11_CLK 86
#define R9A09G011_TIM12_CLK 87
#define R9A09G011_TIM13_CLK 88
#define R9A09G011_TIM14_CLK 89
#define R9A09G011_TIM15_CLK 90
#define R9A09G011_IIC_PCLK1 91
#define R9A09G011_CPERI_GRPC_PCLK 92
#define R9A09G011_TIM16_CLK 93
#define R9A09G011_TIM17_CLK 94
#define R9A09G011_TIM18_CLK 95
#define R9A09G011_TIM19_CLK 96
#define R9A09G011_TIM20_CLK 97
#define R9A09G011_TIM21_CLK 98
#define R9A09G011_TIM22_CLK 99
#define R9A09G011_TIM23_CLK 100
#define R9A09G011_WDT0_PCLK 101
#define R9A09G011_WDT0_CLK 102
#define R9A09G011_WDT1_PCLK 103
#define R9A09G011_WDT1_CLK 104
#define R9A09G011_CPERI_GRPD_PCLK 105
#define R9A09G011_TIM24_CLK 106
#define R9A09G011_TIM25_CLK 107
#define R9A09G011_TIM26_CLK 108
#define R9A09G011_TIM27_CLK 109
#define R9A09G011_TIM28_CLK 110
#define R9A09G011_TIM29_CLK 111
#define R9A09G011_TIM30_CLK 112
#define R9A09G011_TIM31_CLK 113
#define R9A09G011_CPERI_GRPE_PCLK 114
#define R9A09G011_PWM0_CLK 115
#define R9A09G011_PWM1_CLK 116
#define R9A09G011_PWM2_CLK 117
#define R9A09G011_PWM3_CLK 118
#define R9A09G011_PWM4_CLK 119
#define R9A09G011_PWM5_CLK 120
#define R9A09G011_PWM6_CLK 121
#define R9A09G011_PWM7_CLK 122
#define R9A09G011_CPERI_GRPF_PCLK 123
#define R9A09G011_PWM8_CLK 124
#define R9A09G011_PWM9_CLK 125
#define R9A09G011_PWM10_CLK 126
#define R9A09G011_PWM11_CLK 127
#define R9A09G011_PWM12_CLK 128
#define R9A09G011_PWM13_CLK 129
#define R9A09G011_PWM14_CLK 130
#define R9A09G011_PWM15_CLK 131
#define R9A09G011_CPERI_GRPG_PCLK 132
#define R9A09G011_CPERI_GRPH_PCLK 133
#define R9A09G011_URT_PCLK 134
#define R9A09G011_URT0_CLK 135
#define R9A09G011_URT1_CLK 136
#define R9A09G011_CSI0_CLK 137
#define R9A09G011_CSI1_CLK 138
#define R9A09G011_CSI2_CLK 139
#define R9A09G011_CSI3_CLK 140
#define R9A09G011_CSI4_CLK 141
#define R9A09G011_CSI5_CLK 142
#define R9A09G011_ICB_ACLK1 143
#define R9A09G011_ICB_GIC_CLK 144
#define R9A09G011_ICB_MPCLK1 145
#define R9A09G011_ICB_SPCLK1 146
#define R9A09G011_ICB_CLK48 147
#define R9A09G011_ICB_CLK48_2 148
#define R9A09G011_ICB_CLK48_3 149
#define R9A09G011_ICB_CLK48_4L 150
#define R9A09G011_ICB_CLK48_4R 151
#define R9A09G011_ICB_CLK48_5 152
#define R9A09G011_ICB_CST_ATB_SB_CLK 153
#define R9A09G011_ICB_CST_CS_CLK 154
#define R9A09G011_ICB_CLK100_1 155
#define R9A09G011_ICB_ETH0_CLK_AXI 156
#define R9A09G011_ICB_DCI_CLKAXI 157
#define R9A09G011_ICB_SYC_CNT_CLK 158
#define R9A09G011_ICB_DRPA_ACLK 159
#define R9A09G011_ICB_RFX_ACLK 160
#define R9A09G011_ICB_RFX_PCLK5 161
#define R9A09G011_ICB_MMC_ACLK 162
#define R9A09G011_ICB_MPCLK3 163
#define R9A09G011_ICB_CIMA_CLK 164
#define R9A09G011_ICB_CIMB_CLK 165
#define R9A09G011_ICB_BIMA_CLK 166
#define R9A09G011_ICB_FCD_CLKAXI 167
#define R9A09G011_ICB_VD_ACLK4 168
#define R9A09G011_ICB_MPCLK4 169
#define R9A09G011_ICB_VCD_PCLK4 170
#define R9A09G011_CA53_CLK 171
#define R9A09G011_CA53_ACLK 172
#define R9A09G011_CA53_APCLK_DBG 173
#define R9A09G011_CST_APB_CA53_CLK 174
#define R9A09G011_CA53_ATCLK 175
#define R9A09G011_CST_CS_CLK 176
#define R9A09G011_CA53_TSCLK 177
#define R9A09G011_CST_TS_CLK 178
#define R9A09G011_CA53_APCLK_REG 179
#define R9A09G011_DRPA_ACLK 180
#define R9A09G011_DRPA_DCLK 181
#define R9A09G011_DRPA_INITCLK 182
#define R9A09G011_RAMB0_ACLK 183
#define R9A09G011_RAMB1_ACLK 184
#define R9A09G011_RAMB2_ACLK 185
#define R9A09G011_RAMB3_ACLK 186
#define R9A09G011_CIMA_CLKAPB 187
#define R9A09G011_CIMA_CLK 188
#define R9A09G011_CIMB_CLK 189
#define R9A09G011_FAFA_CLK 190
#define R9A09G011_STG_CLKAXI 191
#define R9A09G011_STG_CLK0 192
#define R9A09G011_BIMA_CLKAPB 193
#define R9A09G011_BIMA_CLK 194
#define R9A09G011_FAFB_CLK 195
#define R9A09G011_FCD_CLK 196
#define R9A09G011_FCD_CLKAXI 197
#define R9A09G011_RIM_CLK 198
#define R9A09G011_VCD_ACLK 199
#define R9A09G011_VCD_PCLK 200
#define R9A09G011_JPG0_CLK 201
#define R9A09G011_JPG0_ACLK 202
#define R9A09G011_MMC_CORE_DDRC_CLK 203
#define R9A09G011_MMC_ACLK 204
#define R9A09G011_MMC_PCLK 205
#define R9A09G011_DDI_APBCLK 206
/* Resets */
#define R9A09G011_SYS_RST_N 0
#define R9A09G011_PFC_PRESETN 1
#define R9A09G011_RAMA_ARESETN 2
#define R9A09G011_ROM_ARESETN 3
#define R9A09G011_DMAA_ARESETN 4
#define R9A09G011_SEC_ARESETN 5
#define R9A09G011_SEC_PRESETN 6
#define R9A09G011_SEC_RSTB 7
#define R9A09G011_TSU0_RESETN 8
#define R9A09G011_TSU1_RESETN 9
#define R9A09G011_PMC_RESET_N 10
#define R9A09G011_CST_NTRST 11
#define R9A09G011_CST_NPOTRST 12
#define R9A09G011_CST_NTRST2 13
#define R9A09G011_CST_CS_RESETN 14
#define R9A09G011_CST_TS_RESETN 15
#define R9A09G011_CST_TRESETN 16
#define R9A09G011_CST_SB_RESETN 17
#define R9A09G011_CST_AHB_RESETN 18
#define R9A09G011_CST_TS_SB_RESETN 19
#define R9A09G011_CST_APB_CA53_RESETN 20
#define R9A09G011_CST_ATB_SB_RESETN 21
#define R9A09G011_SDI0_IXRST 22
#define R9A09G011_SDI1_IXRST 23
#define R9A09G011_EMM_IXRST 24
#define R9A09G011_NFI_MARESETN 25
#define R9A09G011_NFI_REG_RST_N 26
#define R9A09G011_USB_PRESET_N 27
#define R9A09G011_USB_DRD_RESET 28
#define R9A09G011_USB_ARESETN_P 29
#define R9A09G011_USB_ARESETN_H 30
#define R9A09G011_ETH0_RST_HW_N 31
#define R9A09G011_PCI_ARESETN 32
#define R9A09G011_SDT_RSTSYSAX 33
#define R9A09G011_GRP_RESETN 34
#define R9A09G011_CIF_RST_N 35
#define R9A09G011_DCU_RSTSYSAX 36
#define R9A09G011_HMI_RST_N 37
#define R9A09G011_HMI_PRESETN 38
#define R9A09G011_LCI_PRESETN 39
#define R9A09G011_LCI_ARESETN 40
#define R9A09G011_AUI_RSTSYSAX 41
#define R9A09G011_MTR_RSTSYSAX 42
#define R9A09G011_GFT_RSTSYSAX 43
#define R9A09G011_ATGA_RSTSYSAX 44
#define R9A09G011_ATGB_RSTSYSAX 45
#define R9A09G011_SYC_RST_N 46
#define R9A09G011_TIM_GPA_PRESETN 47
#define R9A09G011_TIM_GPB_PRESETN 48
#define R9A09G011_TIM_GPC_PRESETN 49
#define R9A09G011_TIM_GPD_PRESETN 50
#define R9A09G011_PWM_GPE_PRESETN 51
#define R9A09G011_PWM_GPF_PRESETN 52
#define R9A09G011_CSI_GPG_PRESETN 53
#define R9A09G011_CSI_GPH_PRESETN 54
#define R9A09G011_IIC_GPA_PRESETN 55
#define R9A09G011_IIC_GPB_PRESETN 56
#define R9A09G011_URT_PRESETN 57
#define R9A09G011_WDT0_PRESETN 58
#define R9A09G011_WDT1_PRESETN 59
#define R9A09G011_ICB_PD_AWO_RST_N 60
#define R9A09G011_ICB_PD_MMC_RST_N 61
#define R9A09G011_ICB_PD_VD0_RST_N 62
#define R9A09G011_ICB_PD_VD1_RST_N 63
#define R9A09G011_ICB_PD_RFX_RST_N 64
#define R9A09G011_CA53_NCPUPORESET0 65
#define R9A09G011_CA53_NCPUPORESET1 66
#define R9A09G011_CA53_NCORERESET0 67
#define R9A09G011_CA53_NCORERESET1 68
#define R9A09G011_CA53_NPRESETDBG 69
#define R9A09G011_CA53_L2RESET 70
#define R9A09G011_CA53_NMISCRESET_HM 71
#define R9A09G011_CA53_NMISCRESET_SM 72
#define R9A09G011_CA53_NARESET 73
#define R9A09G011_DRPA_ARESETN 74
#define R9A09G011_RAMB0_ARESETN 75
#define R9A09G011_RAMB1_ARESETN 76
#define R9A09G011_RAMB2_ARESETN 77
#define R9A09G011_RAMB3_ARESETN 78
#define R9A09G011_CIMA_RSTSYSAX 79
#define R9A09G011_CIMB_RSTSYSAX 80
#define R9A09G011_FAFA_RSTSYSAX 81
#define R9A09G011_STG_RSTSYSAX 82
#define R9A09G011_BIMA_RSTSYSAX 83
#define R9A09G011_FAFB_RSTSYSAX 84
#define R9A09G011_FCD_RSTSYSAX 85
#define R9A09G011_RIM_RSTSYSAX 86
#define R9A09G011_VCD_RESETN 87
#define R9A09G011_JPG_XRESET 88
#define R9A09G011_MMC_CORE_DDRC_RSTN 89
#define R9A09G011_MMC_ARESETN_N 90
#define R9A09G011_MMC_PRESETN 91
#define R9A09G011_DDI_PWROK 92
#define R9A09G011_DDI_RESET 93
#define R9A09G011_DDI_RESETN_APB 94
#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
* Author: Chanho Park <chanho61.park@samsung.com>
*
* Device Tree binding constants for Exynos Auto V9 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
/* CMU_TOP */
#define FOUT_SHARED0_PLL 1
#define FOUT_SHARED1_PLL 2
#define FOUT_SHARED2_PLL 3
#define FOUT_SHARED3_PLL 4
#define FOUT_SHARED4_PLL 5
/* MUX in CMU_TOP */
#define MOUT_SHARED0_PLL 6
#define MOUT_SHARED1_PLL 7
#define MOUT_SHARED2_PLL 8
#define MOUT_SHARED3_PLL 9
#define MOUT_SHARED4_PLL 10
#define MOUT_CLKCMU_CMU_BOOST 11
#define MOUT_CLKCMU_CMU_CMUREF 12
#define MOUT_CLKCMU_ACC_BUS 13
#define MOUT_CLKCMU_APM_BUS 14
#define MOUT_CLKCMU_AUD_CPU 15
#define MOUT_CLKCMU_AUD_BUS 16
#define MOUT_CLKCMU_BUSC_BUS 17
#define MOUT_CLKCMU_BUSMC_BUS 19
#define MOUT_CLKCMU_CORE_BUS 20
#define MOUT_CLKCMU_CPUCL0_SWITCH 21
#define MOUT_CLKCMU_CPUCL0_CLUSTER 22
#define MOUT_CLKCMU_CPUCL1_SWITCH 24
#define MOUT_CLKCMU_CPUCL1_CLUSTER 25
#define MOUT_CLKCMU_DPTX_BUS 26
#define MOUT_CLKCMU_DPTX_DPGTC 27
#define MOUT_CLKCMU_DPUM_BUS 28
#define MOUT_CLKCMU_DPUS0_BUS 29
#define MOUT_CLKCMU_DPUS1_BUS 30
#define MOUT_CLKCMU_FSYS0_BUS 31
#define MOUT_CLKCMU_FSYS0_PCIE 32
#define MOUT_CLKCMU_FSYS1_BUS 33
#define MOUT_CLKCMU_FSYS1_USBDRD 34
#define MOUT_CLKCMU_FSYS1_MMC_CARD 35
#define MOUT_CLKCMU_FSYS2_BUS 36
#define MOUT_CLKCMU_FSYS2_UFS_EMBD 37
#define MOUT_CLKCMU_FSYS2_ETHERNET 38
#define MOUT_CLKCMU_G2D_G2D 39
#define MOUT_CLKCMU_G2D_MSCL 40
#define MOUT_CLKCMU_G3D00_SWITCH 41
#define MOUT_CLKCMU_G3D01_SWITCH 42
#define MOUT_CLKCMU_G3D1_SWITCH 43
#define MOUT_CLKCMU_ISPB_BUS 44
#define MOUT_CLKCMU_MFC_MFC 45
#define MOUT_CLKCMU_MFC_WFD 46
#define MOUT_CLKCMU_MIF_SWITCH 47
#define MOUT_CLKCMU_MIF_BUSP 48
#define MOUT_CLKCMU_NPU_BUS 49
#define MOUT_CLKCMU_PERIC0_BUS 50
#define MOUT_CLKCMU_PERIC0_IP 51
#define MOUT_CLKCMU_PERIC1_BUS 52
#define MOUT_CLKCMU_PERIC1_IP 53
#define MOUT_CLKCMU_PERIS_BUS 54
/* DIV in CMU_TOP */
#define DOUT_SHARED0_DIV3 101
#define DOUT_SHARED0_DIV2 102
#define DOUT_SHARED1_DIV3 103
#define DOUT_SHARED1_DIV2 104
#define DOUT_SHARED1_DIV4 105
#define DOUT_SHARED2_DIV3 106
#define DOUT_SHARED2_DIV2 107
#define DOUT_SHARED2_DIV4 108
#define DOUT_SHARED4_DIV2 109
#define DOUT_SHARED4_DIV4 110
#define DOUT_CLKCMU_CMU_BOOST 111
#define DOUT_CLKCMU_ACC_BUS 112
#define DOUT_CLKCMU_APM_BUS 113
#define DOUT_CLKCMU_AUD_CPU 114
#define DOUT_CLKCMU_AUD_BUS 115
#define DOUT_CLKCMU_BUSC_BUS 116
#define DOUT_CLKCMU_BUSMC_BUS 118
#define DOUT_CLKCMU_CORE_BUS 119
#define DOUT_CLKCMU_CPUCL0_SWITCH 120
#define DOUT_CLKCMU_CPUCL0_CLUSTER 121
#define DOUT_CLKCMU_CPUCL1_SWITCH 123
#define DOUT_CLKCMU_CPUCL1_CLUSTER 124
#define DOUT_CLKCMU_DPTX_BUS 125
#define DOUT_CLKCMU_DPTX_DPGTC 126
#define DOUT_CLKCMU_DPUM_BUS 127
#define DOUT_CLKCMU_DPUS0_BUS 128
#define DOUT_CLKCMU_DPUS1_BUS 129
#define DOUT_CLKCMU_FSYS0_BUS 130
#define DOUT_CLKCMU_FSYS0_PCIE 131
#define DOUT_CLKCMU_FSYS1_BUS 132
#define DOUT_CLKCMU_FSYS1_USBDRD 133
#define DOUT_CLKCMU_FSYS2_BUS 134
#define DOUT_CLKCMU_FSYS2_UFS_EMBD 135
#define DOUT_CLKCMU_FSYS2_ETHERNET 136
#define DOUT_CLKCMU_G2D_G2D 137
#define DOUT_CLKCMU_G2D_MSCL 138
#define DOUT_CLKCMU_G3D00_SWITCH 139
#define DOUT_CLKCMU_G3D01_SWITCH 140
#define DOUT_CLKCMU_G3D1_SWITCH 141
#define DOUT_CLKCMU_ISPB_BUS 142
#define DOUT_CLKCMU_MFC_MFC 143
#define DOUT_CLKCMU_MFC_WFD 144
#define DOUT_CLKCMU_MIF_SWITCH 145
#define DOUT_CLKCMU_MIF_BUSP 146
#define DOUT_CLKCMU_NPU_BUS 147
#define DOUT_CLKCMU_PERIC0_BUS 148
#define DOUT_CLKCMU_PERIC0_IP 149
#define DOUT_CLKCMU_PERIC1_BUS 150
#define DOUT_CLKCMU_PERIC1_IP 151
#define DOUT_CLKCMU_PERIS_BUS 152
/* GAT in CMU_TOP */
#define GOUT_CLKCMU_CMU_BOOST 201
#define GOUT_CLKCMU_CPUCL0_BOOST 202
#define GOUT_CLKCMU_CPUCL1_BOOST 203
#define GOUT_CLKCMU_CORE_BOOST 204
#define GOUT_CLKCMU_BUSC_BOOST 205
#define GOUT_CLKCMU_BUSMC_BOOST 206
#define GOUT_CLKCMU_MIF_BOOST 207
#define GOUT_CLKCMU_ACC_BUS 208
#define GOUT_CLKCMU_APM_BUS 209
#define GOUT_CLKCMU_AUD_CPU 210
#define GOUT_CLKCMU_AUD_BUS 211
#define GOUT_CLKCMU_BUSC_BUS 212
#define GOUT_CLKCMU_BUSMC_BUS 214
#define GOUT_CLKCMU_CORE_BUS 215
#define GOUT_CLKCMU_CPUCL0_SWITCH 216
#define GOUT_CLKCMU_CPUCL0_CLUSTER 217
#define GOUT_CLKCMU_CPUCL1_SWITCH 219
#define GOUT_CLKCMU_CPUCL1_CLUSTER 220
#define GOUT_CLKCMU_DPTX_BUS 221
#define GOUT_CLKCMU_DPTX_DPGTC 222
#define GOUT_CLKCMU_DPUM_BUS 223
#define GOUT_CLKCMU_DPUS0_BUS 224
#define GOUT_CLKCMU_DPUS1_BUS 225
#define GOUT_CLKCMU_FSYS0_BUS 226
#define GOUT_CLKCMU_FSYS0_PCIE 227
#define GOUT_CLKCMU_FSYS1_BUS 228
#define GOUT_CLKCMU_FSYS1_USBDRD 229
#define GOUT_CLKCMU_FSYS1_MMC_CARD 230
#define GOUT_CLKCMU_FSYS2_BUS 231
#define GOUT_CLKCMU_FSYS2_UFS_EMBD 232
#define GOUT_CLKCMU_FSYS2_ETHERNET 233
#define GOUT_CLKCMU_G2D_G2D 234
#define GOUT_CLKCMU_G2D_MSCL 235
#define GOUT_CLKCMU_G3D00_SWITCH 236
#define GOUT_CLKCMU_G3D01_SWITCH 237
#define GOUT_CLKCMU_G3D1_SWITCH 238
#define GOUT_CLKCMU_ISPB_BUS 239
#define GOUT_CLKCMU_MFC_MFC 240
#define GOUT_CLKCMU_MFC_WFD 241
#define GOUT_CLKCMU_MIF_SWITCH 242
#define GOUT_CLKCMU_MIF_BUSP 243
#define GOUT_CLKCMU_NPU_BUS 244
#define GOUT_CLKCMU_PERIC0_BUS 245
#define GOUT_CLKCMU_PERIC0_IP 246
#define GOUT_CLKCMU_PERIC1_BUS 247
#define GOUT_CLKCMU_PERIC1_IP 248
#define GOUT_CLKCMU_PERIS_BUS 249
#define TOP_NR_CLK 250
/* CMU_BUSMC */
#define CLK_MOUT_BUSMC_BUS_USER 1
#define CLK_DOUT_BUSMC_BUSP 2
#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
#define BUSMC_NR_CLK 5
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_DOUT_CORE_BUSP 2
#define CLK_GOUT_CORE_CCI_CLK 3
#define CLK_GOUT_CORE_CCI_PCLK 4
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
#define CORE_NR_CLK 6
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
#define CLK_MOUT_FSYS2_ETHERNET_USER 3
#define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4
#define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5
#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
#define FSYS2_NR_CLK 8
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_IP_USER 2
#define CLK_MOUT_PERIC0_USI00_USI 3
#define CLK_MOUT_PERIC0_USI01_USI 4
#define CLK_MOUT_PERIC0_USI02_USI 5
#define CLK_MOUT_PERIC0_USI03_USI 6
#define CLK_MOUT_PERIC0_USI04_USI 7
#define CLK_MOUT_PERIC0_USI05_USI 8
#define CLK_MOUT_PERIC0_USI_I2C 9
#define CLK_DOUT_PERIC0_USI00_USI 10
#define CLK_DOUT_PERIC0_USI01_USI 11
#define CLK_DOUT_PERIC0_USI02_USI 12
#define CLK_DOUT_PERIC0_USI03_USI 13
#define CLK_DOUT_PERIC0_USI04_USI 14
#define CLK_DOUT_PERIC0_USI05_USI 15
#define CLK_DOUT_PERIC0_USI_I2C 16
#define CLK_GOUT_PERIC0_IPCLK_0 20
#define CLK_GOUT_PERIC0_IPCLK_1 21
#define CLK_GOUT_PERIC0_IPCLK_2 22
#define CLK_GOUT_PERIC0_IPCLK_3 23
#define CLK_GOUT_PERIC0_IPCLK_4 24
#define CLK_GOUT_PERIC0_IPCLK_5 25
#define CLK_GOUT_PERIC0_IPCLK_6 26
#define CLK_GOUT_PERIC0_IPCLK_7 27
#define CLK_GOUT_PERIC0_IPCLK_8 28
#define CLK_GOUT_PERIC0_IPCLK_9 29
#define CLK_GOUT_PERIC0_IPCLK_10 30
#define CLK_GOUT_PERIC0_IPCLK_11 30
#define CLK_GOUT_PERIC0_PCLK_0 31
#define CLK_GOUT_PERIC0_PCLK_1 32
#define CLK_GOUT_PERIC0_PCLK_2 33
#define CLK_GOUT_PERIC0_PCLK_3 34
#define CLK_GOUT_PERIC0_PCLK_4 35
#define CLK_GOUT_PERIC0_PCLK_5 36
#define CLK_GOUT_PERIC0_PCLK_6 37
#define CLK_GOUT_PERIC0_PCLK_7 38
#define CLK_GOUT_PERIC0_PCLK_8 39
#define CLK_GOUT_PERIC0_PCLK_9 40
#define CLK_GOUT_PERIC0_PCLK_10 41
#define CLK_GOUT_PERIC0_PCLK_11 42
#define PERIC0_NR_CLK 43
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
#define CLK_MOUT_PERIC1_IP_USER 2
#define CLK_MOUT_PERIC1_USI06_USI 3
#define CLK_MOUT_PERIC1_USI07_USI 4
#define CLK_MOUT_PERIC1_USI08_USI 5
#define CLK_MOUT_PERIC1_USI09_USI 6
#define CLK_MOUT_PERIC1_USI10_USI 7
#define CLK_MOUT_PERIC1_USI11_USI 8
#define CLK_MOUT_PERIC1_USI_I2C 9
#define CLK_DOUT_PERIC1_USI06_USI 10
#define CLK_DOUT_PERIC1_USI07_USI 11
#define CLK_DOUT_PERIC1_USI08_USI 12
#define CLK_DOUT_PERIC1_USI09_USI 13
#define CLK_DOUT_PERIC1_USI10_USI 14
#define CLK_DOUT_PERIC1_USI11_USI 15
#define CLK_DOUT_PERIC1_USI_I2C 16
#define CLK_GOUT_PERIC1_IPCLK_0 20
#define CLK_GOUT_PERIC1_IPCLK_1 21
#define CLK_GOUT_PERIC1_IPCLK_2 22
#define CLK_GOUT_PERIC1_IPCLK_3 23
#define CLK_GOUT_PERIC1_IPCLK_4 24
#define CLK_GOUT_PERIC1_IPCLK_5 25
#define CLK_GOUT_PERIC1_IPCLK_6 26
#define CLK_GOUT_PERIC1_IPCLK_7 27
#define CLK_GOUT_PERIC1_IPCLK_8 28
#define CLK_GOUT_PERIC1_IPCLK_9 29
#define CLK_GOUT_PERIC1_IPCLK_10 30
#define CLK_GOUT_PERIC1_IPCLK_11 30
#define CLK_GOUT_PERIC1_PCLK_0 31
#define CLK_GOUT_PERIC1_PCLK_1 32
#define CLK_GOUT_PERIC1_PCLK_2 33
#define CLK_GOUT_PERIC1_PCLK_3 34
#define CLK_GOUT_PERIC1_PCLK_4 35
#define CLK_GOUT_PERIC1_PCLK_5 36
#define CLK_GOUT_PERIC1_PCLK_6 37
#define CLK_GOUT_PERIC1_PCLK_7 38
#define CLK_GOUT_PERIC1_PCLK_8 39
#define CLK_GOUT_PERIC1_PCLK_9 40
#define CLK_GOUT_PERIC1_PCLK_10 41
#define CLK_GOUT_PERIC1_PCLK_11 42
#define PERIC1_NR_CLK 43
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_GOUT_SYSREG_PERIS_PCLK 2
#define CLK_GOUT_WDT_CLUSTER0 3
#define CLK_GOUT_WDT_CLUSTER1 4
#define PERIS_NR_CLK 5
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */

17
include/dt-bindings/clock/ste-db8500-clkout.h Normal file
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@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __STE_CLK_DB8500_CLKOUT_H__
#define __STE_CLK_DB8500_CLKOUT_H__
#define DB8500_CLKOUT_1 0
#define DB8500_CLKOUT_2 1
#define DB8500_CLKOUT_SRC_CLK38M 0
#define DB8500_CLKOUT_SRC_ACLK 1
#define DB8500_CLKOUT_SRC_SYSCLK 2
#define DB8500_CLKOUT_SRC_LCDCLK 3
#define DB8500_CLKOUT_SRC_SDMMCCLK 4
#define DB8500_CLKOUT_SRC_TVCLK 5
#define DB8500_CLKOUT_SRC_TIMCLK 6
#define DB8500_CLKOUT_SRC_CLK009 7
#endif

46
include/dt-bindings/clock/stm32mp1-clks.h
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@ -249,30 +249,26 @@
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_PLL2_Q 5
#define CK_SCMI0_PLL2_R 6
#define CK_SCMI0_MPU 7
#define CK_SCMI0_AXI 8
#define CK_SCMI0_BSEC 9
#define CK_SCMI0_CRYP1 10
#define CK_SCMI0_GPIOZ 11
#define CK_SCMI0_HASH1 12
#define CK_SCMI0_I2C4 13
#define CK_SCMI0_I2C6 14
#define CK_SCMI0_IWDG1 15
#define CK_SCMI0_RNG1 16
#define CK_SCMI0_RTC 17
#define CK_SCMI0_RTCAPB 18
#define CK_SCMI0_SPI6 19
#define CK_SCMI0_USART1 20
#define CK_SCMI1_PLL3_Q 0
#define CK_SCMI1_PLL3_R 1
#define CK_SCMI1_MCU 2
#define CK_SCMI_HSE 0
#define CK_SCMI_HSI 1
#define CK_SCMI_CSI 2
#define CK_SCMI_LSE 3
#define CK_SCMI_LSI 4
#define CK_SCMI_PLL2_Q 5
#define CK_SCMI_PLL2_R 6
#define CK_SCMI_MPU 7
#define CK_SCMI_AXI 8
#define CK_SCMI_BSEC 9
#define CK_SCMI_CRYP1 10
#define CK_SCMI_GPIOZ 11
#define CK_SCMI_HASH1 12
#define CK_SCMI_I2C4 13
#define CK_SCMI_I2C6 14
#define CK_SCMI_IWDG1 15
#define CK_SCMI_RNG1 16
#define CK_SCMI_RTC 17
#define CK_SCMI_RTCAPB 18
#define CK_SCMI_SPI6 19
#define CK_SCMI_USART1 20
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

229
include/dt-bindings/clock/stm32mp13-clks.h Normal file
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@ -0,0 +1,229 @@
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
#define _DT_BINDINGS_STM32MP13_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* PLL */
#define PLL1 6
#define PLL2 7
#define PLL3 8
#define PLL4 9
/* ODF */
#define PLL1_P 10
#define PLL1_Q 11
#define PLL1_R 12
#define PLL2_P 13
#define PLL2_Q 14
#define PLL2_R 15
#define PLL3_P 16
#define PLL3_Q 17
#define PLL3_R 18
#define PLL4_P 19
#define PLL4_Q 20
#define PLL4_R 21
#define PCLK1 22
#define PCLK2 23
#define PCLK3 24
#define PCLK4 25
#define PCLK5 26
#define PCLK6 27
/* SYSTEM CLOCK */
#define CK_PER 28
#define CK_MPU 29
#define CK_AXI 30
#define CK_MLAHB 31
/* BASE TIMER */
#define CK_TIMG1 32
#define CK_TIMG2 33
#define CK_TIMG3 34
/* AUX */
#define RTC 35
/* TRACE & DEBUG clocks */
#define CK_DBG 36
#define CK_TRACE 37
/* MCO clocks */
#define CK_MCO1 38
#define CK_MCO2 39
/* IP clocks */
#define SYSCFG 40
#define VREF 41
#define DTS 42
#define PMBCTRL 43
#define HDP 44
#define IWDG2 45
#define STGENRO 46
#define USART1 47
#define RTCAPB 48
#define TZC 49
#define TZPC 50
#define IWDG1 51
#define BSEC 52
#define DMA1 53
#define DMA2 54
#define DMAMUX1 55
#define DMAMUX2 56
#define GPIOA 57
#define GPIOB 58
#define GPIOC 59
#define GPIOD 60
#define GPIOE 61
#define GPIOF 62
#define GPIOG 63
#define GPIOH 64
#define GPIOI 65
#define CRYP1 66
#define HASH1 67
#define BKPSRAM 68
#define MDMA 69
#define CRC1 70
#define USBH 71
#define DMA3 72
#define TSC 73
#define PKA 74
#define AXIMC 75
#define MCE 76
#define ETH1TX 77
#define ETH2TX 78
#define ETH1RX 79
#define ETH2RX 80
#define ETH1MAC 81
#define ETH2MAC 82
#define ETH1STP 83
#define ETH2STP 84
/* IP clocks with parents */
#define SDMMC1_K 85
#define SDMMC2_K 86
#define ADC1_K 87
#define ADC2_K 88
#define FMC_K 89
#define QSPI_K 90
#define RNG1_K 91
#define USBPHY_K 92
#define STGEN_K 93
#define SPDIF_K 94
#define SPI1_K 95
#define SPI2_K 96
#define SPI3_K 97
#define SPI4_K 98
#define SPI5_K 99
#define I2C1_K 100
#define I2C2_K 101
#define I2C3_K 102
#define I2C4_K 103
#define I2C5_K 104
#define TIM2_K 105
#define TIM3_K 106
#define TIM4_K 107
#define TIM5_K 108
#define TIM6_K 109
#define TIM7_K 110
#define TIM12_K 111
#define TIM13_K 112
#define TIM14_K 113
#define TIM1_K 114
#define TIM8_K 115
#define TIM15_K 116
#define TIM16_K 117
#define TIM17_K 118
#define LPTIM1_K 119
#define LPTIM2_K 120
#define LPTIM3_K 121
#define LPTIM4_K 122
#define LPTIM5_K 123
#define USART1_K 124
#define USART2_K 125
#define USART3_K 126
#define UART4_K 127
#define UART5_K 128
#define USART6_K 129
#define UART7_K 130
#define UART8_K 131
#define DFSDM_K 132
#define FDCAN_K 133
#define SAI1_K 134
#define SAI2_K 135
#define ADFSDM_K 136
#define USBO_K 137
#define LTDC_PX 138
#define ETH1CK_K 139
#define ETH1PTP_K 140
#define ETH2CK_K 141
#define ETH2PTP_K 142
#define DCMIPP_K 143
#define SAES_K 144
#define DTS_K 145
/* DDR */
#define DDRC1 146
#define DDRC1LP 147
#define DDRC2 148
#define DDRC2LP 149
#define DDRPHYC 150
#define DDRPHYCLP 151
#define DDRCAPB 152
#define DDRCAPBLP 153
#define AXIDCG 154
#define DDRPHYCAPB 155
#define DDRPHYCAPBLP 156
#define DDRPERFM 157
#define ADC1 158
#define ADC2 159
#define SAI1 160
#define SAI2 161
#define STM32MP1_LAST_CLK 162
/* SCMI clock identifiers */
#define CK_SCMI_HSE 0
#define CK_SCMI_HSI 1
#define CK_SCMI_CSI 2
#define CK_SCMI_LSE 3
#define CK_SCMI_LSI 4
#define CK_SCMI_HSE_DIV2 5
#define CK_SCMI_PLL2_Q 6
#define CK_SCMI_PLL2_R 7
#define CK_SCMI_PLL3_P 8
#define CK_SCMI_PLL3_Q 9
#define CK_SCMI_PLL3_R 10
#define CK_SCMI_PLL4_P 11
#define CK_SCMI_PLL4_Q 12
#define CK_SCMI_PLL4_R 13
#define CK_SCMI_MPU 14
#define CK_SCMI_AXI 15
#define CK_SCMI_MLAHB 16
#define CK_SCMI_CKPER 17
#define CK_SCMI_PCLK1 18
#define CK_SCMI_PCLK2 19
#define CK_SCMI_PCLK3 20
#define CK_SCMI_PCLK4 21
#define CK_SCMI_PCLK5 22
#define CK_SCMI_PCLK6 23
#define CK_SCMI_CKTIMG1 24
#define CK_SCMI_CKTIMG2 25
#define CK_SCMI_CKTIMG3 26
#define CK_SCMI_RTC 27
#define CK_SCMI_RTCAPB 28
#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */

1
include/dt-bindings/clock/sun50i-h6-r-ccu.h
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@ -22,5 +22,6 @@
#define CLK_W1 12
#define CLK_R_APB2_RSB 13
#define CLK_R_APB1_RTC 14
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

1
include/dt-bindings/clock/sun50i-h616-ccu.h
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@ -111,5 +111,6 @@
#define CLK_BUS_TVE0 125
#define CLK_HDCP 126
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */

8
include/dt-bindings/clock/tegra234-clock.h
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@ -140,6 +140,14 @@
#define TEGRA234_CLK_PEX2_C9_CORE 173U
/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
#define TEGRA234_CLK_PEX2_C10_CORE 187U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */
#define TEGRA234_CLK_QSPI0_2X_PM 192U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */
#define TEGRA234_CLK_QSPI1_2X_PM 193U
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */
#define TEGRA234_CLK_QSPI0_PM 194U
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */
#define TEGRA234_CLK_QSPI1_PM 195U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
/** @brief output of gate CLK_ENB_PEX0_CORE_0 */

421
include/dt-bindings/gce/mt8186-gce.h Normal file
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@ -0,0 +1,421 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Yongqiang Niu <yongqiang.niu@mediatek.com>
*/
#ifndef _DT_BINDINGS_GCE_MT8186_H
#define _DT_BINDINGS_GCE_MT8186_H
/* assign timeout 0 also means default */
#define CMDQ_NO_TIMEOUT 0xffffffff
#define CMDQ_TIMEOUT_DEFAULT 1000
/* GCE thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_1 1
#define CMDQ_THR_PRIO_2 2
#define CMDQ_THR_PRIO_3 3
#define CMDQ_THR_PRIO_4 4
#define CMDQ_THR_PRIO_5 5
#define CMDQ_THR_PRIO_6 6
#define CMDQ_THR_PRIO_HIGHEST 7
/* CPR count in 32bit register */
#define GCE_CPR_COUNT 1312
/* GCE subsys table */
#define SUBSYS_1300XXXX 0
#define SUBSYS_1400XXXX 1
#define SUBSYS_1401XXXX 2
#define SUBSYS_1402XXXX 3
#define SUBSYS_1502XXXX 4
#define SUBSYS_1582XXXX 5
#define SUBSYS_1B00XXXX 6
#define SUBSYS_1C00XXXX 7
#define SUBSYS_1C10XXXX 8
#define SUBSYS_1000XXXX 9
#define SUBSYS_1001XXXX 10
#define SUBSYS_1020XXXX 11
#define SUBSYS_1021XXXX 12
#define SUBSYS_1022XXXX 13
#define SUBSYS_1023XXXX 14
#define SUBSYS_1060XXXX 15
#define SUBSYS_1602XXXX 16
#define SUBSYS_1608XXXX 17
#define SUBSYS_1700XXXX 18
#define SUBSYS_1701XXXX 19
#define SUBSYS_1702XXXX 20
#define SUBSYS_1703XXXX 21
#define SUBSYS_1706XXXX 22
#define SUBSYS_1A00XXXX 23
#define SUBSYS_1A01XXXX 24
#define SUBSYS_1A02XXXX 25
#define SUBSYS_1A03XXXX 26
#define SUBSYS_1A04XXXX 27
#define SUBSYS_1A05XXXX 28
#define SUBSYS_1A06XXXX 29
#define SUBSYS_NO_SUPPORT 99
/* GCE General Purpose Register (GPR) support
* Leave note for scenario usage here
*/
/* GCE: write mask */
#define GCE_GPR_R00 0x00
#define GCE_GPR_R01 0x01
/* MDP: P1: JPEG dest */
#define GCE_GPR_R02 0x02
#define GCE_GPR_R03 0x03
/* MDP: PQ color */
#define GCE_GPR_R04 0x04
/* MDP: 2D sharpness */
#define GCE_GPR_R05 0x05
/* DISP: poll esd */
#define GCE_GPR_R06 0x06
#define GCE_GPR_R07 0x07
/* MDP: P4: 2D sharpness dst */
#define GCE_GPR_R08 0x08
#define GCE_GPR_R09 0x09
/* VCU: poll with timeout for GPR timer */
#define GCE_GPR_R10 0x0A
#define GCE_GPR_R11 0x0B
/* CMDQ: debug */
#define GCE_GPR_R12 0x0C
#define GCE_GPR_R13 0x0D
/* CMDQ: P7: debug */
#define GCE_GPR_R14 0x0E
#define GCE_GPR_R15 0x0F
/* GCE hardware events */
/* VDEC */
#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0
#define CMDQ_EVENT_VDEC_INT 1
#define CMDQ_EVENT_VDEC_PAUSE 2
#define CMDQ_EVENT_VDEC_DEC_ERROR 3
#define CMDQ_EVENT_MDEC_TIMEOUT 4
#define CMDQ_EVENT_DRAM_ACCESS_DONE 5
#define CMDQ_EVENT_INI_FETCH_RDY 6
#define CMDQ_EVENT_PROCESS_FLAG 7
#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8
#define CMDQ_EVENT_REF_REORDER_DONE 9
#define CMDQ_EVENT_WP_TBLE_DONE 10
#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11
#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30
#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31
#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32
/* CAM */
#define CMDQ_EVENT_ISP_FRAME_DONE_A 65
#define CMDQ_EVENT_ISP_FRAME_DONE_B 66
#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70
#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71
#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72
#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75
#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76
#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77
#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78
#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79
#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80
#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81
#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82
#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83
#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84
#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85
#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86
#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87
#define CMDQ_EVENT_TG_OVRUN_A_INT 88
#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89
#define CMDQ_EVENT_TG_OVRUN_B_INT 90
#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91
#define CMDQ_EVENT_TG_OVRUN_M0_INT 94
#define CMDQ_EVENT_R1_ERROR_M0_INT 95
#define CMDQ_EVENT_TG_GRABERR_M0_INT 96
#define CMDQ_EVENT_TG_GRABERR_A_INT 98
#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99
#define CMDQ_EVENT_TG_GRABERR_B_INT 100
#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101
/* VENC */
#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129
#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130
#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131
#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132
#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133
#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136
#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137
#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138
/* IPE */
#define CMDQ_EVENT_FDVT_DONE 161
#define CMDQ_EVENT_FE_DONE 162
#define CMDQ_EVENT_RSC_DONE 163
#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164
#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165
/* IMG2 */
#define CMDQ_EVENT_GCE_IMG2_EVENT0 193
#define CMDQ_EVENT_GCE_IMG2_EVENT1 194
#define CMDQ_EVENT_GCE_IMG2_EVENT2 195
#define CMDQ_EVENT_GCE_IMG2_EVENT3 196
#define CMDQ_EVENT_GCE_IMG2_EVENT4 197
#define CMDQ_EVENT_GCE_IMG2_EVENT5 198
#define CMDQ_EVENT_GCE_IMG2_EVENT6 199
#define CMDQ_EVENT_GCE_IMG2_EVENT7 200
#define CMDQ_EVENT_GCE_IMG2_EVENT8 201
#define CMDQ_EVENT_GCE_IMG2_EVENT9 202
#define CMDQ_EVENT_GCE_IMG2_EVENT10 203
#define CMDQ_EVENT_GCE_IMG2_EVENT11 204
#define CMDQ_EVENT_GCE_IMG2_EVENT12 205
#define CMDQ_EVENT_GCE_IMG2_EVENT13 206
#define CMDQ_EVENT_GCE_IMG2_EVENT14 207
#define CMDQ_EVENT_GCE_IMG2_EVENT15 208
#define CMDQ_EVENT_GCE_IMG2_EVENT16 209
#define CMDQ_EVENT_GCE_IMG2_EVENT17 210
#define CMDQ_EVENT_GCE_IMG2_EVENT18 211
#define CMDQ_EVENT_GCE_IMG2_EVENT19 212
#define CMDQ_EVENT_GCE_IMG2_EVENT20 213
#define CMDQ_EVENT_GCE_IMG2_EVENT21 214
#define CMDQ_EVENT_GCE_IMG2_EVENT22 215
#define CMDQ_EVENT_GCE_IMG2_EVENT23 216
/* IMG1 */
#define CMDQ_EVENT_GCE_IMG1_EVENT0 225
#define CMDQ_EVENT_GCE_IMG1_EVENT1 226
#define CMDQ_EVENT_GCE_IMG1_EVENT2 227
#define CMDQ_EVENT_GCE_IMG1_EVENT3 228
#define CMDQ_EVENT_GCE_IMG1_EVENT4 229
#define CMDQ_EVENT_GCE_IMG1_EVENT5 230
#define CMDQ_EVENT_GCE_IMG1_EVENT6 231
#define CMDQ_EVENT_GCE_IMG1_EVENT7 232
#define CMDQ_EVENT_GCE_IMG1_EVENT8 233
#define CMDQ_EVENT_GCE_IMG1_EVENT9 234
#define CMDQ_EVENT_GCE_IMG1_EVENT10 235
#define CMDQ_EVENT_GCE_IMG1_EVENT11 236
#define CMDQ_EVENT_GCE_IMG1_EVENT12 237
#define CMDQ_EVENT_GCE_IMG1_EVENT13 238
#define CMDQ_EVENT_GCE_IMG1_EVENT14 239
#define CMDQ_EVENT_GCE_IMG1_EVENT15 240
#define CMDQ_EVENT_GCE_IMG1_EVENT16 241
#define CMDQ_EVENT_GCE_IMG1_EVENT17 242
#define CMDQ_EVENT_GCE_IMG1_EVENT18 243
#define CMDQ_EVENT_GCE_IMG1_EVENT19 244
#define CMDQ_EVENT_GCE_IMG1_EVENT20 245
#define CMDQ_EVENT_GCE_IMG1_EVENT21 246
#define CMDQ_EVENT_GCE_IMG1_EVENT22 247
#define CMDQ_EVENT_GCE_IMG1_EVENT23 248
/* MDP */
#define CMDQ_EVENT_MDP_RDMA0_SOF 256
#define CMDQ_EVENT_MDP_RDMA1_SOF 257
#define CMDQ_EVENT_MDP_AAL0_SOF 258
#define CMDQ_EVENT_MDP_AAL1_SOF 259
#define CMDQ_EVENT_MDP_HDR0_SOF 260
#define CMDQ_EVENT_MDP_RSZ0_SOF 261
#define CMDQ_EVENT_MDP_RSZ1_SOF 262
#define CMDQ_EVENT_MDP_WROT0_SOF 263
#define CMDQ_EVENT_MDP_WROT1_SOF 264
#define CMDQ_EVENT_MDP_TDSHP0_SOF 265
#define CMDQ_EVENT_MDP_TDSHP1_SOF 266
#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267
#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268
#define CMDQ_EVENT_MDP_COLOR0_SOF 269
#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288
#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289
#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290
#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291
#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292
#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293
#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294
#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295
#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296
#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297
#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298
#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299
#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300
#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301
#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302
#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303
#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304
#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305
#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306
#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307
#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308
#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309
#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334
#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335
#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336
#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337
#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338
#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339
#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340
#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341
#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342
#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343
/* DISP */
#define CMDQ_EVENT_DISP_OVL0_SOF 384
#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385
#define CMDQ_EVENT_DISP_RDMA0_SOF 386
#define CMDQ_EVENT_DISP_RSZ0_SOF 387
#define CMDQ_EVENT_DISP_COLOR0_SOF 388
#define CMDQ_EVENT_DISP_CCORR0_SOF 389
#define CMDQ_EVENT_DISP_CCORR1_SOF 390
#define CMDQ_EVENT_DISP_AAL0_SOF 391
#define CMDQ_EVENT_DISP_GAMMA0_SOF 392
#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393
#define CMDQ_EVENT_DISP_DITHER0_SOF 394
#define CMDQ_EVENT_DISP_CM0_SOF 395
#define CMDQ_EVENT_DISP_SPR0_SOF 396
#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397
#define CMDQ_EVENT_DSI0_SOF 398
#define CMDQ_EVENT_DISP_WDMA0_SOF 399
#define CMDQ_EVENT_DISP_PWM0_SOF 400
#define CMDQ_EVENT_DSI0_FRAME_DONE 410
#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411
#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412
#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413
#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414
#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415
#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416
#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417
#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418
#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420
#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421
#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422
#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423
#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424
#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425
#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448
#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449
#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450
#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451
#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452
#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453
#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454
#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455
#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456
#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465
#define CMDQ_EVENT_OUT_EVENT_0 898
/* CMDQ sw tokens
* Following definitions are gce sw token which may use by clients
* event operation API.
* Note that token 512 to 639 may set secure
*/
/* end of hw event and begin of sw token */
#define CMDQ_MAX_HW_EVENT 512
/* Config thread notify trigger thread */
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
/* Trigger thread notify config thread */
#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
/* Block Trigger thread until the ESD check finishes. */
#define CMDQ_SYNC_TOKEN_ESD_EOF 642
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
/* check CABC setup finish */
#define CMDQ_SYNC_TOKEN_CABC_EOF 644
/* Notify normal CMDQ there are some secure task done
* MUST NOT CHANGE, this token sync with secure world
*/
#define CMDQ_SYNC_SECURE_THR_EOF 647
/* CMDQ use sw token */
#define CMDQ_SYNC_TOKEN_USER_0 649
#define CMDQ_SYNC_TOKEN_USER_1 650
#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
/* ISP sw token */
#define CMDQ_SYNC_TOKEN_MSS 665
#define CMDQ_SYNC_TOKEN_MSF 666
/* DISP sw token */
#define CMDQ_SYNC_TOKEN_SODI 671
/* GPR access tokens (for register backup)
* There are 15 32-bit GPR, 3 GPR form a set
* (64-bit for address, 32-bit for value)
* MUST NOT CHANGE, these tokens sync with MDP
*/
#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
/* Resource lock event to control resource in GCE thread */
#define CMDQ_SYNC_RESOURCE_WROT0 710
#define CMDQ_SYNC_RESOURCE_WROT1 711
/* event for gpr timer, used in sleep and poll with timeout */
#define CMDQ_TOKEN_GPR_TIMER_R0 994
#define CMDQ_TOKEN_GPR_TIMER_R1 995
#define CMDQ_TOKEN_GPR_TIMER_R2 996
#define CMDQ_TOKEN_GPR_TIMER_R3 997
#define CMDQ_TOKEN_GPR_TIMER_R4 998
#define CMDQ_TOKEN_GPR_TIMER_R5 999
#define CMDQ_TOKEN_GPR_TIMER_R6 1000
#define CMDQ_TOKEN_GPR_TIMER_R7 1001
#define CMDQ_TOKEN_GPR_TIMER_R8 1002
#define CMDQ_TOKEN_GPR_TIMER_R9 1003
#define CMDQ_TOKEN_GPR_TIMER_R10 1004
#define CMDQ_TOKEN_GPR_TIMER_R11 1005
#define CMDQ_TOKEN_GPR_TIMER_R12 1006
#define CMDQ_TOKEN_GPR_TIMER_R13 1007
#define CMDQ_TOKEN_GPR_TIMER_R14 1008
#define CMDQ_TOKEN_GPR_TIMER_R15 1009
#define CMDQ_EVENT_MAX 0x3FF
/* CMDQ sw tokens END */
#endif

7
include/dt-bindings/interconnect/qcom,sc8180x.h
View file

@ -182,4 +182,11 @@
#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3
#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define SLAVE_QUP_CORE_0 3
#define SLAVE_QUP_CORE_1 4
#define SLAVE_QUP_CORE_2 5
#endif

232
include/dt-bindings/interconnect/qcom,sc8280xp.h Normal file
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@ -0,0 +1,232 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Ltd.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H
/* aggre1_noc */
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_QUP_2 2
#define MASTER_A1NOC_CFG 3
#define MASTER_IPA 4
#define MASTER_EMAC_1 5
#define MASTER_SDCC_4 6
#define MASTER_UFS_MEM 7
#define MASTER_USB3_0 8
#define MASTER_USB3_1 9
#define MASTER_USB3_MP 10
#define MASTER_USB4_0 11
#define MASTER_USB4_1 12
#define SLAVE_A1NOC_SNOC 13
#define SLAVE_USB_NOC_SNOC 14
#define SLAVE_SERVICE_A1NOC 15
/* aggre2_noc */
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_0 1
#define MASTER_A2NOC_CFG 2
#define MASTER_CRYPTO 3
#define MASTER_SENSORS_PROC 4
#define MASTER_SP 5
#define MASTER_EMAC 6
#define MASTER_PCIE_0 7
#define MASTER_PCIE_1 8
#define MASTER_PCIE_2A 9
#define MASTER_PCIE_2B 10
#define MASTER_PCIE_3A 11
#define MASTER_PCIE_3B 12
#define MASTER_PCIE_4 13
#define MASTER_QDSS_ETR 14
#define MASTER_SDCC_2 15
#define MASTER_UFS_CARD 16
#define SLAVE_A2NOC_SNOC 17
#define SLAVE_ANOC_PCIE_GEM_NOC 18
#define SLAVE_SERVICE_A2NOC 19
/* clk_virt */
#define MASTER_IPA_CORE 0
#define MASTER_QUP_CORE_0 1
#define MASTER_QUP_CORE_1 2
#define MASTER_QUP_CORE_2 3
#define SLAVE_IPA_CORE 4
#define SLAVE_QUP_CORE_0 5
#define SLAVE_QUP_CORE_1 6
#define SLAVE_QUP_CORE_2 7
/* config_noc */
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AHB2PHY_0 2
#define SLAVE_AHB2PHY_1 3
#define SLAVE_AHB2PHY_2 4
#define SLAVE_AOSS 5
#define SLAVE_APPSS 6
#define SLAVE_CAMERA_CFG 7
#define SLAVE_CLK_CTL 8
#define SLAVE_CDSP_CFG 9
#define SLAVE_CDSP1_CFG 10
#define SLAVE_RBCPR_CX_CFG 11
#define SLAVE_RBCPR_MMCX_CFG 12
#define SLAVE_RBCPR_MX_CFG 13
#define SLAVE_CPR_NSPCX 14
#define SLAVE_CRYPTO_0_CFG 15
#define SLAVE_CX_RDPM 16
#define SLAVE_DCC_CFG 17
#define SLAVE_DISPLAY_CFG 18
#define SLAVE_DISPLAY1_CFG 19
#define SLAVE_EMAC_CFG 20
#define SLAVE_EMAC1_CFG 21
#define SLAVE_GFX3D_CFG 22
#define SLAVE_HWKM 23
#define SLAVE_IMEM_CFG 24
#define SLAVE_IPA_CFG 25
#define SLAVE_IPC_ROUTER_CFG 26
#define SLAVE_LPASS 27
#define SLAVE_MX_RDPM 28
#define SLAVE_MXC_RDPM 29
#define SLAVE_PCIE_0_CFG 30
#define SLAVE_PCIE_1_CFG 31
#define SLAVE_PCIE_2A_CFG 32
#define SLAVE_PCIE_2B_CFG 33
#define SLAVE_PCIE_3A_CFG 34
#define SLAVE_PCIE_3B_CFG 35
#define SLAVE_PCIE_4_CFG 36
#define SLAVE_PCIE_RSC_CFG 37
#define SLAVE_PDM 38
#define SLAVE_PIMEM_CFG 39
#define SLAVE_PKA_WRAPPER_CFG 40
#define SLAVE_PMU_WRAPPER_CFG 41
#define SLAVE_QDSS_CFG 42
#define SLAVE_QSPI_0 43
#define SLAVE_QUP_0 44
#define SLAVE_QUP_1 45
#define SLAVE_QUP_2 46
#define SLAVE_SDCC_2 47
#define SLAVE_SDCC_4 48
#define SLAVE_SECURITY 49
#define SLAVE_SMMUV3_CFG 50
#define SLAVE_SMSS_CFG 51
#define SLAVE_SPSS_CFG 52
#define SLAVE_TCSR 53
#define SLAVE_TLMM 54
#define SLAVE_UFS_CARD_CFG 55
#define SLAVE_UFS_MEM_CFG 56
#define SLAVE_USB3_0 57
#define SLAVE_USB3_1 58
#define SLAVE_USB3_MP 59
#define SLAVE_USB4_0 60
#define SLAVE_USB4_1 61
#define SLAVE_VENUS_CFG 62
#define SLAVE_VSENSE_CTRL_CFG 63
#define SLAVE_VSENSE_CTRL_R_CFG 64
#define SLAVE_A1NOC_CFG 65
#define SLAVE_A2NOC_CFG 66
#define SLAVE_ANOC_PCIE_BRIDGE_CFG 67
#define SLAVE_DDRSS_CFG 68
#define SLAVE_CNOC_MNOC_CFG 69
#define SLAVE_SNOC_CFG 70
#define SLAVE_SNOC_SF_BRIDGE_CFG 71
#define SLAVE_IMEM 72
#define SLAVE_PIMEM 73
#define SLAVE_SERVICE_CNOC 74
#define SLAVE_PCIE_0 75
#define SLAVE_PCIE_1 76
#define SLAVE_PCIE_2A 77
#define SLAVE_PCIE_2B 78
#define SLAVE_PCIE_3A 79
#define SLAVE_PCIE_3B 80
#define SLAVE_PCIE_4 81
#define SLAVE_QDSS_STM 82
#define SLAVE_SMSS 83
#define SLAVE_TCU 84
/* dc_noc */
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LLCC_CFG 1
#define SLAVE_GEM_NOC_CFG 2
/* gem_noc */
#define MASTER_GPU_TCU 0
#define MASTER_PCIE_TCU 1
#define MASTER_SYS_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_COMPUTE_NOC 4
#define MASTER_COMPUTE_NOC_1 5
#define MASTER_GEM_NOC_CFG 6
#define MASTER_GFX3D 7
#define MASTER_MNOC_HF_MEM_NOC 8
#define MASTER_MNOC_SF_MEM_NOC 9
#define MASTER_ANOC_PCIE_GEM_NOC 10
#define MASTER_SNOC_GC_MEM_NOC 11
#define MASTER_SNOC_SF_MEM_NOC 12
#define SLAVE_GEM_NOC_CNOC 13
#define SLAVE_LLCC 14
#define SLAVE_GEM_NOC_PCIE_CNOC 15
#define SLAVE_SERVICE_GEM_NOC_1 16
#define SLAVE_SERVICE_GEM_NOC_2 17
#define SLAVE_SERVICE_GEM_NOC 18
/* lpass_ag_noc */
#define MASTER_CNOC_LPASS_AG_NOC 0
#define MASTER_LPASS_PROC 1
#define SLAVE_LPASS_CORE_CFG 2
#define SLAVE_LPASS_LPI_CFG 3
#define SLAVE_LPASS_MPU_CFG 4
#define SLAVE_LPASS_TOP_CFG 5
#define SLAVE_LPASS_SNOC 6
#define SLAVE_SERVICES_LPASS_AML_NOC 7
#define SLAVE_SERVICE_LPASS_AG_NOC 8
/* mc_virt */
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
/*mmss_noc */
#define MASTER_CAMNOC_HF 0
#define MASTER_MDP0 1
#define MASTER_MDP1 2
#define MASTER_MDP_CORE1_0 3
#define MASTER_MDP_CORE1_1 4
#define MASTER_CNOC_MNOC_CFG 5
#define MASTER_ROTATOR 6
#define MASTER_ROTATOR_1 7
#define MASTER_VIDEO_P0 8
#define MASTER_VIDEO_P1 9
#define MASTER_VIDEO_PROC 10
#define MASTER_CAMNOC_ICP 11
#define MASTER_CAMNOC_SF 12
#define SLAVE_MNOC_HF_MEM_NOC 13
#define SLAVE_MNOC_SF_MEM_NOC 14
#define SLAVE_SERVICE_MNOC 15
/* nspa_noc */
#define MASTER_CDSP_NOC_CFG 0
#define MASTER_CDSP_PROC 1
#define SLAVE_CDSP_MEM_NOC 2
#define SLAVE_NSP_XFR 3
#define SLAVE_SERVICE_NSP_NOC 4
/* nspb_noc */
#define MASTER_CDSPB_NOC_CFG 0
#define MASTER_CDSP_PROC_B 1
#define SLAVE_CDSPB_MEM_NOC 2
#define SLAVE_NSPB_XFR 3
#define SLAVE_SERVICE_NSPB_NOC 4
/* system_noc */
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define MASTER_USB_NOC_SNOC 2
#define MASTER_LPASS_ANOC 3
#define MASTER_SNOC_CFG 4
#define MASTER_PIMEM 5
#define MASTER_GIC 6
#define SLAVE_SNOC_GEM_NOC_GC 7
#define SLAVE_SNOC_GEM_NOC_SF 8
#define SLAVE_SERVICE_SNOC 9
#endif

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include/dt-bindings/interconnect/qcom,sdx65.h Normal file
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@ -0,0 +1,67 @@
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_TCU_0 0
#define MASTER_SNOC_GC_MEM_NOC 1
#define MASTER_APPSS_PROC 2
#define SLAVE_LLCC 3
#define SLAVE_MEM_NOC_SNOC 4
#define SLAVE_MEM_NOC_PCIE_SNOC 5
#define MASTER_AUDIO 0
#define MASTER_BLSP_1 1
#define MASTER_QDSS_BAM 2
#define MASTER_QPIC 3
#define MASTER_SNOC_CFG 4
#define MASTER_SPMI_FETCHER 5
#define MASTER_ANOC_SNOC 6
#define MASTER_IPA 7
#define MASTER_MEM_NOC_SNOC 8
#define MASTER_MEM_NOC_PCIE_SNOC 9
#define MASTER_CRYPTO 10
#define MASTER_IPA_PCIE 11
#define MASTER_PCIE_0 12
#define MASTER_QDSS_ETR 13
#define MASTER_SDCC_1 14
#define MASTER_USB3 15
#define SLAVE_AOSS 16
#define SLAVE_APPSS 17
#define SLAVE_AUDIO 18
#define SLAVE_BLSP_1 19
#define SLAVE_CLK_CTL 20
#define SLAVE_CRYPTO_0_CFG 21
#define SLAVE_CNOC_DDRSS 22
#define SLAVE_ECC_CFG 23
#define SLAVE_IMEM_CFG 24
#define SLAVE_IPA_CFG 25
#define SLAVE_CNOC_MSS 26
#define SLAVE_PCIE_PARF 27
#define SLAVE_PDM 28
#define SLAVE_PRNG 29
#define SLAVE_QDSS_CFG 30
#define SLAVE_QPIC 31
#define SLAVE_SDCC_1 32
#define SLAVE_SNOC_CFG 33
#define SLAVE_SPMI_FETCHER 34
#define SLAVE_SPMI_VGI_COEX 35
#define SLAVE_TCSR 36
#define SLAVE_TLMM 37
#define SLAVE_USB3 38
#define SLAVE_USB3_PHY_CFG 39
#define SLAVE_ANOC_SNOC 40
#define SLAVE_SNOC_MEM_NOC_GC 41
#define SLAVE_IMEM 42
#define SLAVE_SERVICE_SNOC 43
#define SLAVE_PCIE_0 44
#define SLAVE_QDSS_STM 45
#define SLAVE_TCU 46
#endif

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include/dt-bindings/mailbox/tegra186-hsp.h
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@ -15,6 +15,11 @@
#define TEGRA_HSP_MBOX_TYPE_SS 0x2
#define TEGRA_HSP_MBOX_TYPE_AS 0x3
/*
* These define the types of shared mailbox supported based on data size.
*/
#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
/*
* These defines represent the bit associated with the given master ID in the
* doorbell registers.

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include/dt-bindings/memory/mt8186-memory-port.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
*
* Author: Anan Sun <anan.sun@mediatek.com>
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
#include <dt-bindings/memory/mtk-memory-port.h>
/*
* MM IOMMU supports 16GB dma address. We separate it to four ranges:
* 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
* locate in anyone region. BUT:
* a) Make sure all the ports inside a larb are in one range.
* b) The iova of any master can NOT cross the 4G/8G/12G boundary.
*
* This is the suggested mapping in this SoC:
*
* modules dma-address-region larbs-ports
* disp 0 ~ 4G larb0/1/2
* vcodec 4G ~ 8G larb4/7
* cam/mdp 8G ~ 12G the other larbs.
* N/A 12G ~ 16G
* CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
* CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
*/
/* MM IOMMU ports */
/* LARB 0 -- MMSYS */
#define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0)
#define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1)
#define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2)
#define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3)
/* LARB 1 -- MMSYS */
#define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0)
#define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1)
#define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2)
#define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3)
#define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4)
/* LARB 2 -- MMSYS */
#define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
#define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1)
#define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2)
#define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3)
#define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4)
/* LARB 4 -- VDEC */
#define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0)
#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1)
#define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2)
#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3)
#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4)
#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5)
#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6)
#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8)
#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10)
#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11)
#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12)
#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13)
/* LARB 7 -- VENC */
#define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0)
#define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1)
#define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2)
#define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3)
#define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4)
#define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5)
#define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6)
#define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7)
#define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8)
#define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9)
#define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10)
#define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11)
#define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12)
/* LARB 8 -- WPE */
#define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0)
#define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1)
#define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2)
/* LARB 9 -- IMG-1 */
#define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0)
#define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1)
#define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2)
#define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3)
#define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4)
#define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5)
#define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6)
#define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7)
#define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8)
#define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9)
#define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10)
#define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11)
#define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12)
#define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13)
#define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14)
#define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15)
#define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16)
#define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17)
#define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18)
#define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19)
#define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20)
#define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21)
#define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22)
#define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23)
#define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24)
#define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25)
#define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26)
#define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27)
#define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28)
/* LARB 11 -- IMG-2 */
#define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0)
#define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1)
#define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2)
#define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3)
#define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4)
#define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5)
#define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6)
#define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7)
#define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8)
#define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9)
#define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10)
#define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11)
#define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12)
#define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13)
#define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14)
#define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15)
#define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16)
#define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17)
#define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18)
#define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19)
#define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20)
#define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21)
#define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22)
#define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23)
#define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24)
#define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25)
#define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26)
#define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27)
#define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28)
/* LARB 13 -- CAM */
#define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0)
#define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1)
#define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2)
#define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6)
#define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7)
#define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8)
#define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9)
#define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10)
#define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11)
/* LARB 14 -- CAM */
#define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4)
#define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5)
/* LARB 16 -- RAW-A */
#define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0)
#define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1)
#define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
#define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3)
#define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4)
#define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5)
#define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6)
#define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7)
#define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
#define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
#define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10)
#define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11)
#define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
#define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13)
#define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14)
#define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15)
#define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16)
/* LARB 17 -- RAW-B */
#define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0)
#define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1)
#define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2)
#define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3)
#define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4)
#define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5)
#define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6)
#define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7)
#define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8)
#define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9)
#define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10)
#define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11)
#define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12)
#define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13)
#define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14)
#define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15)
#define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16)
/* LARB 19 -- IPE */
#define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0)
#define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1)
#define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2)
#define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3)
/* LARB 20 -- IPE */
#define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0)
#define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1)
#define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2)
#define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3)
#define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4)
#define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5)
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
#include <dt-bindings/memory/mtk-memory-port.h>
/*
* MM IOMMU supports 16GB dma address. We separate it to four ranges:
* 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
* locate in anyone region. BUT:
* a) Make sure all the ports inside a larb are in one range.
* b) The iova of any master can NOT cross the 4G/8G/12G boundary.
*
* This is the suggested mapping in this SoC:
*
* modules dma-address-region larbs-ports
* disp 0 ~ 4G larb0/1/2/3
* vcodec 4G ~ 8G larb19/20/21/22/23/24
* cam/mdp 8G ~ 12G the other larbs.
* N/A 12G ~ 16G
* CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1
* CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
*
* This SoC have two IOMMU HWs, this is the detailed connected information:
* iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
* iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
*/
/* MM IOMMU ports */
/* larb0 */
#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)
#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1)
#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2)
#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)
#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4)
#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
/* larb1 */
#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0)
#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1)
#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2)
#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3)
#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4)
#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5)
/* larb2 */
#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1)
#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2)
#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3)
#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4)
/* larb3 */
#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0)
#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1)
#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2)
#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3)
#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4)
#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5)
#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6)
/* larb4 */
#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0)
#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1)
#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2)
#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3)
#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4)
/* larb5 */
#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)
#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1)
#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2)
#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3)
#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4)
#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5)
#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6)
#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7)
/* larb6 */
#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0)
#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1)
#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2)
#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3)
/* larb7 */
#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)
#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1)
#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2)
/* larb8 */
#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0)
#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1)
#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2)
/* larb9 */
#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1)
#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2)
#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3)
#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4)
#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5)
#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6)
#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7)
#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8)
#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9)
#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)
#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11)
#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12)
#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13)
#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14)
#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15)
#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16)
#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17)
#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18)
#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
/* larb10 */
#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1)
#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2)
#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3)
#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4)
#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5)
#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6)
#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7)
#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8)
#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9)
#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10)
#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11)
#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12)
#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13)
#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14)
#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15)
#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16)
#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17)
#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18)
#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20)
#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21)
#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22)
#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23)
/* larb11 */
#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)
#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1)
#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2)
#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3)
#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4)
#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5)
#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6)
#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7)
#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8)
#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9)
/* larb12 */
#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0)
#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1)
#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2)
#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3)
#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4)
#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5)
#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6)
#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7)
#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8)
#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9)
/* larb13 */
#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0)
#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1)
#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2)
#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3)
#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4)
#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5)
#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6)
#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7)
#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8)
#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9)
/* larb14 */
#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0)
#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1)
#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2)
#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3)
#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4)
#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5)
#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6)
#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7)
#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8)
#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9)
#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10)
#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11)
#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12)
#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13)
#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14)
/* larb15: null */
/* larb16 */
#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0)
#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1)
#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2)
#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3)
#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4)
#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5)
#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6)
#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7)
#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8)
#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9)
#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10)
#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11)
#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12)
#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13)
#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14)
#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15)
/* larb17 */
#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0)
#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1)
#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2)
#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3)
#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4)
#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5)
#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6)
/* larb18 */
#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)
#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1)
#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2)
#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3)
/* larb19 */
#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)
#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)
#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)
#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)
#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)
#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7)
#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8)
#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)
#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)
#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)
#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12)
#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13)
#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14)
#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15)
#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16)
#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17)
#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18)
#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19)
#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20)
#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)
#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22)
#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23)
#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)
#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)
#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26)
/* larb20 */
#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0)
#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1)
#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2)
#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3)
#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4)
#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5)
#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6)
#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7)
#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8)
#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9)
#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10)
#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11)
#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12)
#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13)
#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14)
#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15)
#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16)
#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17)
#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18)
#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19)
#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20)
#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21)
#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22)
#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23)
#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24)
#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25)
#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26)
/* larb21 */
#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0)
#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1)
#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2)
#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3)
#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4)
#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5)
#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6)
#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7)
#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8)
#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9)
/* larb22 */
#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0)
#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1)
#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2)
#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3)
#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4)
#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5)
#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6)
#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7)
#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8)
#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9)
/* larb23 */
#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0)
#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1)
/* larb24 */
#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0)
#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1)
#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2)
#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3)
#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4)
#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5)
#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6)
#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7)
#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8)
#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9)
#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10)
#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11)
/* larb25 */
#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)
#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1)
#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2)
#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3)
#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4)
#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5)
#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6)
#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7)
#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8)
#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9)
#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10)
#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11)
/* larb26 */
#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0)
#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1)
#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2)
#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3)
#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4)
#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5)
#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6)
#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7)
#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8)
#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9)
#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10)
#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11)
/* larb27 */
#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1)
#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2)
#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3)
#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4)
#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)
#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6)
#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7)
#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8)
#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9)
#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10)
#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11)
#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12)
#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13)
#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14)
#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15)
/* larb28 */
#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0)
#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1)
#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2)
#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3)
#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4)
#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5)
#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6)
/* Infra iommu ports */
/* PCIe1: read: BIT16; write BIT17. */
#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16)
/* PCIe0: read: BIT18; write BIT19. */
#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18)
#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20)
#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21)
#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22)
#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23)
#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24)
#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25)
#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26)
#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27)
#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28)
#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29)
#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30)
#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31)
#endif

2
include/dt-bindings/memory/mtk-memory-port.h
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@ -12,4 +12,6 @@
#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
#define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port)
#endif

18
include/dt-bindings/mfd/cros_ec.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* DTS binding definitions used for the Chromium OS Embedded Controller.
*
* Copyright (c) 2022 The Chromium OS Authors. All rights reserved.
*/
#ifndef _DT_BINDINGS_MFD_CROS_EC_H
#define _DT_BINDINGS_MFD_CROS_EC_H
/* Typed channel for keyboard backlight. */
#define CROS_EC_PWM_DT_KB_LIGHT 0
/* Typed channel for display backlight. */
#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1
/* Number of typed channels. */
#define CROS_EC_PWM_DT_COUNT 2
#endif

908
include/dt-bindings/pinctrl/mt6795-pinfunc.h Normal file
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@ -0,0 +1,908 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __DTS_MT8173_PINFUNC_H
#define __DTS_MT8173_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define PINMUX_GPIO0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1)
#define PINMUX_GPIO0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2)
#define PINMUX_GPIO0__FUNC_TDD_TMS (MTK_PIN_NO(0) | 4)
#define PINMUX_GPIO0__FUNC_UTXD0 (MTK_PIN_NO(0) | 5)
#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define PINMUX_GPIO1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1)
#define PINMUX_GPIO1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2)
#define PINMUX_GPIO1__FUNC_SDA4 (MTK_PIN_NO(1) | 3)
#define PINMUX_GPIO1__FUNC_TDD_TCK (MTK_PIN_NO(1) | 4)
#define PINMUX_GPIO1__FUNC_URXD0 (MTK_PIN_NO(1) | 5)
#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define PINMUX_GPIO2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1)
#define PINMUX_GPIO2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2)
#define PINMUX_GPIO2__FUNC_SCL4 (MTK_PIN_NO(2) | 3)
#define PINMUX_GPIO2__FUNC_TDD_TDI (MTK_PIN_NO(2) | 4)
#define PINMUX_GPIO2__FUNC_UTXD3 (MTK_PIN_NO(2) | 5)
#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define PINMUX_GPIO3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1)
#define PINMUX_GPIO3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2)
#define PINMUX_GPIO3__FUNC_SDA3 (MTK_PIN_NO(3) | 3)
#define PINMUX_GPIO3__FUNC_TDD_TDO (MTK_PIN_NO(3) | 4)
#define PINMUX_GPIO3__FUNC_URXD3 (MTK_PIN_NO(3) | 5)
#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define PINMUX_GPIO4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1)
#define PINMUX_GPIO4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2)
#define PINMUX_GPIO4__FUNC_SCL3 (MTK_PIN_NO(4) | 3)
#define PINMUX_GPIO4__FUNC_TDD_TRSTN (MTK_PIN_NO(4) | 4)
#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1)
#define PINMUX_GPIO5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2)
#define PINMUX_GPIO5__FUNC_SPI_CK_3 (MTK_PIN_NO(5) | 3)
#define PINMUX_GPIO5__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(5) | 4)
#define PINMUX_GPIO5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5)
#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1)
#define PINMUX_GPIO6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2)
#define PINMUX_GPIO6__FUNC_SPI_MI_3 (MTK_PIN_NO(6) | 3)
#define PINMUX_GPIO6__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(6) | 4)
#define PINMUX_GPIO6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5)
#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define PINMUX_GPIO7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1)
#define PINMUX_GPIO7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2)
#define PINMUX_GPIO7__FUNC_SPI_MO_3 (MTK_PIN_NO(7) | 3)
#define PINMUX_GPIO7__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(7) | 4)
#define PINMUX_GPIO7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5)
#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define PINMUX_GPIO8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1)
#define PINMUX_GPIO8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2)
#define PINMUX_GPIO8__FUNC_SPI_CS_3 (MTK_PIN_NO(8) | 3)
#define PINMUX_GPIO8__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(8) | 4)
#define PINMUX_GPIO8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5)
#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 1)
#define PINMUX_GPIO9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2)
#define PINMUX_GPIO9__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(9) | 4)
#define PINMUX_GPIO9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5)
#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define PINMUX_GPIO10__FUNC_I2S0_WS (MTK_PIN_NO(10) | 2)
#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 2)
#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define PINMUX_GPIO12__FUNC_I2S0_MCK (MTK_PIN_NO(12) | 2)
#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define PINMUX_GPIO13__FUNC_I2S0_DO (MTK_PIN_NO(13) | 2)
#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define PINMUX_GPIO14__FUNC_I2S0_DI (MTK_PIN_NO(14) | 2)
#define PINMUX_GPIO14__FUNC_DISP_PWM1 (MTK_PIN_NO(14) | 3)
#define PINMUX_GPIO14__FUNC_PWM4 (MTK_PIN_NO(14) | 4)
#define PINMUX_GPIO14__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5)
#define PINMUX_GPIO14__FUNC_I2S1_BCK (MTK_PIN_NO(14) | 6)
#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define PINMUX_GPIO15__FUNC_DSI1_TE (MTK_PIN_NO(15) | 2)
#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3)
#define PINMUX_GPIO15__FUNC_PWM5 (MTK_PIN_NO(15) | 4)
#define PINMUX_GPIO15__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5)
#define PINMUX_GPIO15__FUNC_I2S1_MCK (MTK_PIN_NO(15) | 6)
#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 1)
#define PINMUX_GPIO16__FUNC_FLASH (MTK_PIN_NO(16) | 2)
#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 3)
#define PINMUX_GPIO16__FUNC_PWM5 (MTK_PIN_NO(16) | 4)
#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define PINMUX_GPIO17__FUNC_SIM1_SCLK (MTK_PIN_NO(17) | 1)
#define PINMUX_GPIO17__FUNC_SIM2_SCLK (MTK_PIN_NO(17) | 2)
#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define PINMUX_GPIO18__FUNC_SIM1_SRST (MTK_PIN_NO(18) | 1)
#define PINMUX_GPIO18__FUNC_SIM2_SRST (MTK_PIN_NO(18) | 2)
#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define PINMUX_GPIO19__FUNC_SIM1_SDAT (MTK_PIN_NO(19) | 1)
#define PINMUX_GPIO19__FUNC_SIM2_SDAT (MTK_PIN_NO(19) | 2)
#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define PINMUX_GPIO20__FUNC_SIM2_SCLK (MTK_PIN_NO(20) | 1)
#define PINMUX_GPIO20__FUNC_SIM1_SCLK (MTK_PIN_NO(20) | 2)
#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define PINMUX_GPIO21__FUNC_SIM2_SRST (MTK_PIN_NO(21) | 1)
#define PINMUX_GPIO21__FUNC_SIM1_SRST (MTK_PIN_NO(21) | 2)
#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define PINMUX_GPIO22__FUNC_SIM2_SDAT (MTK_PIN_NO(22) | 1)
#define PINMUX_GPIO22__FUNC_SIM1_SDAT (MTK_PIN_NO(22) | 2)
#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define PINMUX_GPIO23__FUNC_MSDC3_DAT0 (MTK_PIN_NO(23) | 1)
#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define PINMUX_GPIO24__FUNC_MSDC3_DAT1 (MTK_PIN_NO(24) | 1)
#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define PINMUX_GPIO25__FUNC_MSDC3_DAT2 (MTK_PIN_NO(25) | 1)
#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define PINMUX_GPIO26__FUNC_MSDC3_DAT3 (MTK_PIN_NO(26) | 1)
#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define PINMUX_GPIO27__FUNC_MSDC3_CLK (MTK_PIN_NO(27) | 1)
#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define PINMUX_GPIO28__FUNC_MSDC3_CMD (MTK_PIN_NO(28) | 1)
#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define PINMUX_GPIO29__FUNC_PTA_RXD (MTK_PIN_NO(29) | 1)
#define PINMUX_GPIO29__FUNC_UCTS2 (MTK_PIN_NO(29) | 2)
#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define PINMUX_GPIO30__FUNC_PTA_TXD (MTK_PIN_NO(30) | 1)
#define PINMUX_GPIO30__FUNC_URTS2 (MTK_PIN_NO(30) | 2)
#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define PINMUX_GPIO31__FUNC_URXD2 (MTK_PIN_NO(31) | 1)
#define PINMUX_GPIO31__FUNC_UTXD2 (MTK_PIN_NO(31) | 2)
#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define PINMUX_GPIO32__FUNC_UTXD2 (MTK_PIN_NO(32) | 1)
#define PINMUX_GPIO32__FUNC_URXD2 (MTK_PIN_NO(32) | 2)
#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define PINMUX_GPIO33__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1)
#define PINMUX_GPIO33__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2)
#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define PINMUX_GPIO34__FUNC_MRG_DI (MTK_PIN_NO(34) | 1)
#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2)
#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define PINMUX_GPIO35__FUNC_MRG_DO (MTK_PIN_NO(35) | 1)
#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2)
#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define PINMUX_GPIO36__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1)
#define PINMUX_GPIO36__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2)
#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define PINMUX_GPIO37__FUNC_GPS_SYNC (MTK_PIN_NO(37) | 1)
#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define PINMUX_GPIO38__FUNC_DAIRSTB (MTK_PIN_NO(38) | 1)
#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define PINMUX_GPIO39__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1)
#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define PINMUX_GPIO40__FUNC_CM3MCLK (MTK_PIN_NO(40) | 1)
#define PINMUX_GPIO40__FUNC_IRDA_PDN (MTK_PIN_NO(40) | 2)
#define PINMUX_GPIO40__FUNC_PWM6 (MTK_PIN_NO(40) | 3)
#define PINMUX_GPIO40__FUNC_I2S1_WS (MTK_PIN_NO(40) | 4)
#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define PINMUX_GPIO41__FUNC_CMPCLK (MTK_PIN_NO(41) | 1)
#define PINMUX_GPIO41__FUNC_CMCSK (MTK_PIN_NO(41) | 2)
#define PINMUX_GPIO41__FUNC_FLASH (MTK_PIN_NO(41) | 3)
#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define PINMUX_GPIO42__FUNC_CMMCLK (MTK_PIN_NO(42) | 1)
#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define PINMUX_GPIO43__FUNC_SDA2 (MTK_PIN_NO(43) | 1)
#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define PINMUX_GPIO44__FUNC_SCL2 (MTK_PIN_NO(44) | 1)
#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define PINMUX_GPIO45__FUNC_SDA0 (MTK_PIN_NO(45) | 1)
#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define PINMUX_GPIO46__FUNC_SCL0 (MTK_PIN_NO(46) | 1)
#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define PINMUX_GPIO47__FUNC_BPI_BUS0 (MTK_PIN_NO(47) | 1)
#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define PINMUX_GPIO48__FUNC_BPI_BUS1 (MTK_PIN_NO(48) | 1)
#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define PINMUX_GPIO49__FUNC_BPI_BUS2 (MTK_PIN_NO(49) | 1)
#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define PINMUX_GPIO50__FUNC_BPI_BUS3 (MTK_PIN_NO(50) | 1)
#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define PINMUX_GPIO51__FUNC_BPI_BUS4 (MTK_PIN_NO(51) | 1)
#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define PINMUX_GPIO52__FUNC_BPI_BUS5 (MTK_PIN_NO(52) | 1)
#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define PINMUX_GPIO53__FUNC_BPI_BUS6 (MTK_PIN_NO(53) | 1)
#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define PINMUX_GPIO54__FUNC_BPI_BUS7 (MTK_PIN_NO(54) | 1)
#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define PINMUX_GPIO58__FUNC_BPI_BUS11 (MTK_PIN_NO(58) | 1)
#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define PINMUX_GPIO59__FUNC_BPI_BUS12 (MTK_PIN_NO(59) | 1)
#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define PINMUX_GPIO60__FUNC_BPI_BUS13 (MTK_PIN_NO(60) | 1)
#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define PINMUX_GPIO61__FUNC_BPI_BUS14 (MTK_PIN_NO(61) | 1)
#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define PINMUX_GPIO62__FUNC_RFIC1_BSI_CK (MTK_PIN_NO(62) | 1)
#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define PINMUX_GPIO63__FUNC_RFIC1_BSI_D0 (MTK_PIN_NO(63) | 1)
#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define PINMUX_GPIO64__FUNC_RFIC1_BSI_D1 (MTK_PIN_NO(64) | 1)
#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define PINMUX_GPIO65__FUNC_RFIC1_BSI_D2 (MTK_PIN_NO(65) | 1)
#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define PINMUX_GPIO66__FUNC_RFIC1_BSI_CS (MTK_PIN_NO(66) | 1)
#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define PINMUX_GPIO67__FUNC_TD_TXBPI (MTK_PIN_NO(67) | 1)
#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define PINMUX_GPIO68__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(68) | 1)
#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define PINMUX_GPIO69__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(69) | 1)
#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define PINMUX_GPIO70__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(70) | 1)
#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define PINMUX_GPIO71__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(71) | 1)
#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define PINMUX_GPIO72__FUNC_RFIC0_BSI_CS (MTK_PIN_NO(72) | 1)
#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define PINMUX_GPIO73__FUNC_MISC_BSI_DO (MTK_PIN_NO(73) | 1)
#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define PINMUX_GPIO74__FUNC_MISC_BSI_CK (MTK_PIN_NO(74) | 1)
#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define PINMUX_GPIO75__FUNC_MISC_BSI_CS0B (MTK_PIN_NO(75) | 1)
#define PINMUX_GPIO75__FUNC_MIPI1_SCLK (MTK_PIN_NO(75) | 2)
#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define PINMUX_GPIO76__FUNC_MISC_BSI_CS1B (MTK_PIN_NO(76) | 1)
#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define PINMUX_GPIO77__FUNC_MISC_BSI_DI (MTK_PIN_NO(77) | 1)
#define PINMUX_GPIO77__FUNC_MIPI1_SDATA (MTK_PIN_NO(77) | 2)
#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define PINMUX_GPIO78__FUNC_LTE_TXBPI (MTK_PIN_NO(78) | 1)
#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define PINMUX_GPIO79__FUNC_BPI_BUS15 (MTK_PIN_NO(79) | 1)
#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define PINMUX_GPIO80__FUNC_BPI_BUS16 (MTK_PIN_NO(80) | 1)
#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define PINMUX_GPIO81__FUNC_BPI_BUS17 (MTK_PIN_NO(81) | 1)
#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define PINMUX_GPIO82__FUNC_BPI_BUS18 (MTK_PIN_NO(82) | 1)
#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define PINMUX_GPIO83__FUNC_BPI_BUS19 (MTK_PIN_NO(83) | 1)
#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define PINMUX_GPIO84__FUNC_BPI_BUS20 (MTK_PIN_NO(84) | 1)
#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
#define PINMUX_GPIO85__FUNC_BPI_BUS21 (MTK_PIN_NO(85) | 1)
#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
#define PINMUX_GPIO86__FUNC_BPI_BUS22 (MTK_PIN_NO(86) | 1)
#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
#define PINMUX_GPIO87__FUNC_BPI_BUS23 (MTK_PIN_NO(87) | 1)
#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
#define PINMUX_GPIO88__FUNC_BPI_BUS24 (MTK_PIN_NO(88) | 1)
#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
#define PINMUX_GPIO89__FUNC_BPI_BUS25 (MTK_PIN_NO(89) | 1)
#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
#define PINMUX_GPIO90__FUNC_BPI_BUS26 (MTK_PIN_NO(90) | 1)
#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
#define PINMUX_GPIO91__FUNC_BPI_BUS27 (MTK_PIN_NO(91) | 1)
#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
#define PINMUX_GPIO92__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1)
#define PINMUX_GPIO92__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2)
#define PINMUX_GPIO92__FUNC_NLD6 (MTK_PIN_NO(92) | 3)
#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
#define PINMUX_GPIO93__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1)
#define PINMUX_GPIO93__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2)
#define PINMUX_GPIO93__FUNC_NLD7 (MTK_PIN_NO(93) | 3)
#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
#define PINMUX_GPIO94__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1)
#define PINMUX_GPIO94__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2)
#define PINMUX_GPIO94__FUNC_NREB (MTK_PIN_NO(94) | 3)
#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define PINMUX_GPIO95__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1)
#define PINMUX_GPIO95__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2)
#define PINMUX_GPIO95__FUNC_NRNB0 (MTK_PIN_NO(95) | 3)
#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
#define PINMUX_GPIO96__FUNC_URXD1 (MTK_PIN_NO(96) | 1)
#define PINMUX_GPIO96__FUNC_UTXD1 (MTK_PIN_NO(96) | 2)
#define PINMUX_GPIO96__FUNC_NWEB (MTK_PIN_NO(96) | 3)
#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
#define PINMUX_GPIO97__FUNC_UTXD1 (MTK_PIN_NO(97) | 1)
#define PINMUX_GPIO97__FUNC_URXD1 (MTK_PIN_NO(97) | 2)
#define PINMUX_GPIO97__FUNC_NCEB0 (MTK_PIN_NO(97) | 3)
#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
#define PINMUX_GPIO98__FUNC_URTS1 (MTK_PIN_NO(98) | 1)
#define PINMUX_GPIO98__FUNC_UCTS1 (MTK_PIN_NO(98) | 2)
#define PINMUX_GPIO98__FUNC_NALE (MTK_PIN_NO(98) | 3)
#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
#define PINMUX_GPIO99__FUNC_UCTS1 (MTK_PIN_NO(99) | 1)
#define PINMUX_GPIO99__FUNC_URTS1 (MTK_PIN_NO(99) | 2)
#define PINMUX_GPIO99__FUNC_NCLE (MTK_PIN_NO(99) | 3)
#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define PINMUX_GPIO100__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1)
#define PINMUX_GPIO100__FUNC_URXD1 (MTK_PIN_NO(100) | 2)
#define PINMUX_GPIO100__FUNC_USB_DRVVBUS (MTK_PIN_NO(100) | 3)
#define PINMUX_GPIO100__FUNC_SDA4 (MTK_PIN_NO(100) | 4)
#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define PINMUX_GPIO101__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1)
#define PINMUX_GPIO101__FUNC_UTXD1 (MTK_PIN_NO(101) | 2)
#define PINMUX_GPIO101__FUNC_SCL4 (MTK_PIN_NO(101) | 4)
#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define PINMUX_GPIO102__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1)
#define PINMUX_GPIO102__FUNC_URTS1 (MTK_PIN_NO(102) | 2)
#define PINMUX_GPIO102__FUNC_UTXD0 (MTK_PIN_NO(102) | 3)
#define PINMUX_GPIO102__FUNC_PWM0 (MTK_PIN_NO(102) | 5)
#define PINMUX_GPIO102__FUNC_SPI_CK_1 (MTK_PIN_NO(102) | 6)
#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define PINMUX_GPIO103__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1)
#define PINMUX_GPIO103__FUNC_UCTS1 (MTK_PIN_NO(103) | 2)
#define PINMUX_GPIO103__FUNC_URXD0 (MTK_PIN_NO(103) | 3)
#define PINMUX_GPIO103__FUNC_PWM1 (MTK_PIN_NO(103) | 5)
#define PINMUX_GPIO103__FUNC_SPI_MI_1 (MTK_PIN_NO(103) | 6)
#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define PINMUX_GPIO104__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1)
#define PINMUX_GPIO104__FUNC_NLD4 (MTK_PIN_NO(104) | 2)
#define PINMUX_GPIO104__FUNC_UTXD3 (MTK_PIN_NO(104) | 3)
#define PINMUX_GPIO104__FUNC_SDA3 (MTK_PIN_NO(104) | 4)
#define PINMUX_GPIO104__FUNC_PWM2 (MTK_PIN_NO(104) | 5)
#define PINMUX_GPIO104__FUNC_SPI_MO_1 (MTK_PIN_NO(104) | 6)
#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define PINMUX_GPIO105__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1)
#define PINMUX_GPIO105__FUNC_NLD5 (MTK_PIN_NO(105) | 2)
#define PINMUX_GPIO105__FUNC_URXD3 (MTK_PIN_NO(105) | 3)
#define PINMUX_GPIO105__FUNC_SCL3 (MTK_PIN_NO(105) | 4)
#define PINMUX_GPIO105__FUNC_PWM3 (MTK_PIN_NO(105) | 5)
#define PINMUX_GPIO105__FUNC_SPI_CS_1 (MTK_PIN_NO(105) | 6)
#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define PINMUX_GPIO106__FUNC_LCM_RST (MTK_PIN_NO(106) | 1)
#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define PINMUX_GPIO107__FUNC_DSI_TE (MTK_PIN_NO(107) | 1)
#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define PINMUX_GPIO108__FUNC_JTMS (MTK_PIN_NO(108) | 1)
#define PINMUX_GPIO108__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2)
#define PINMUX_GPIO108__FUNC_TDD_TMS (MTK_PIN_NO(108) | 3)
#define PINMUX_GPIO108__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(108) | 4)
#define PINMUX_GPIO108__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5)
#define PINMUX_GPIO108__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6)
#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define PINMUX_GPIO109__FUNC_JTCK (MTK_PIN_NO(109) | 1)
#define PINMUX_GPIO109__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2)
#define PINMUX_GPIO109__FUNC_TDD_TCK (MTK_PIN_NO(109) | 3)
#define PINMUX_GPIO109__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(109) | 4)
#define PINMUX_GPIO109__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5)
#define PINMUX_GPIO109__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6)
#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define PINMUX_GPIO110__FUNC_JTDI (MTK_PIN_NO(110) | 1)
#define PINMUX_GPIO110__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2)
#define PINMUX_GPIO110__FUNC_TDD_TDI (MTK_PIN_NO(110) | 3)
#define PINMUX_GPIO110__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(110) | 4)
#define PINMUX_GPIO110__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5)
#define PINMUX_GPIO110__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6)
#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define PINMUX_GPIO111__FUNC_JTDO (MTK_PIN_NO(111) | 1)
#define PINMUX_GPIO111__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2)
#define PINMUX_GPIO111__FUNC_TDD_TDO (MTK_PIN_NO(111) | 3)
#define PINMUX_GPIO111__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(111) | 4)
#define PINMUX_GPIO111__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5)
#define PINMUX_GPIO111__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6)
#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define PINMUX_GPIO112__FUNC_JTRST_B (MTK_PIN_NO(112) | 1)
#define PINMUX_GPIO112__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2)
#define PINMUX_GPIO112__FUNC_TDD_TRSTN (MTK_PIN_NO(112) | 3)
#define PINMUX_GPIO112__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(112) | 4)
#define PINMUX_GPIO112__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5)
#define PINMUX_GPIO112__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6)
#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define PINMUX_GPIO113__FUNC_URXD0 (MTK_PIN_NO(113) | 1)
#define PINMUX_GPIO113__FUNC_UTXD0 (MTK_PIN_NO(113) | 2)
#define PINMUX_GPIO113__FUNC_MD_URXD (MTK_PIN_NO(113) | 3)
#define PINMUX_GPIO113__FUNC_LTE_URXD (MTK_PIN_NO(113) | 4)
#define PINMUX_GPIO113__FUNC_TDD_TXD (MTK_PIN_NO(113) | 5)
#define PINMUX_GPIO113__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6)
#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define PINMUX_GPIO114__FUNC_UTXD0 (MTK_PIN_NO(114) | 1)
#define PINMUX_GPIO114__FUNC_URXD0 (MTK_PIN_NO(114) | 2)
#define PINMUX_GPIO114__FUNC_MD_UTXD (MTK_PIN_NO(114) | 3)
#define PINMUX_GPIO114__FUNC_LTE_UTXD (MTK_PIN_NO(114) | 4)
#define PINMUX_GPIO114__FUNC_TDD_TXD (MTK_PIN_NO(114) | 5)
#define PINMUX_GPIO114__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6)
#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define PINMUX_GPIO115__FUNC_URTS0 (MTK_PIN_NO(115) | 1)
#define PINMUX_GPIO115__FUNC_UCTS0 (MTK_PIN_NO(115) | 2)
#define PINMUX_GPIO115__FUNC_MD_URXD (MTK_PIN_NO(115) | 3)
#define PINMUX_GPIO115__FUNC_LTE_URXD (MTK_PIN_NO(115) | 4)
#define PINMUX_GPIO115__FUNC_TDD_TXD (MTK_PIN_NO(115) | 5)
#define PINMUX_GPIO115__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6)
#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define PINMUX_GPIO116__FUNC_UCTS0 (MTK_PIN_NO(116) | 1)
#define PINMUX_GPIO116__FUNC_URTS0 (MTK_PIN_NO(116) | 2)
#define PINMUX_GPIO116__FUNC_MD_UTXD (MTK_PIN_NO(116) | 3)
#define PINMUX_GPIO116__FUNC_LTE_UTXD (MTK_PIN_NO(116) | 4)
#define PINMUX_GPIO116__FUNC_TDD_TXD (MTK_PIN_NO(116) | 5)
#define PINMUX_GPIO116__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6)
#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define PINMUX_GPIO117__FUNC_URXD3 (MTK_PIN_NO(117) | 1)
#define PINMUX_GPIO117__FUNC_UTXD3 (MTK_PIN_NO(117) | 2)
#define PINMUX_GPIO117__FUNC_MD_URXD (MTK_PIN_NO(117) | 3)
#define PINMUX_GPIO117__FUNC_LTE_URXD (MTK_PIN_NO(117) | 4)
#define PINMUX_GPIO117__FUNC_TDD_TXD (MTK_PIN_NO(117) | 5)
#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define PINMUX_GPIO118__FUNC_UTXD3 (MTK_PIN_NO(118) | 1)
#define PINMUX_GPIO118__FUNC_URXD3 (MTK_PIN_NO(118) | 2)
#define PINMUX_GPIO118__FUNC_MD_UTXD (MTK_PIN_NO(118) | 3)
#define PINMUX_GPIO118__FUNC_LTE_UTXD (MTK_PIN_NO(118) | 4)
#define PINMUX_GPIO118__FUNC_TDD_TXD (MTK_PIN_NO(118) | 5)
#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define PINMUX_GPIO119__FUNC_KROW0 (MTK_PIN_NO(119) | 1)
#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define PINMUX_GPIO120__FUNC_KROW1 (MTK_PIN_NO(120) | 1)
#define PINMUX_GPIO120__FUNC_PWM6 (MTK_PIN_NO(120) | 3)
#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define PINMUX_GPIO121__FUNC_KROW2 (MTK_PIN_NO(121) | 1)
#define PINMUX_GPIO121__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2)
#define PINMUX_GPIO121__FUNC_I2S1_DO_1 (MTK_PIN_NO(121) | 3)
#define PINMUX_GPIO121__FUNC_USB_DRVVBUS (MTK_PIN_NO(121) | 4)
#define PINMUX_GPIO121__FUNC_SPI_CK_2 (MTK_PIN_NO(121) | 5)
#define PINMUX_GPIO121__FUNC_PWM4 (MTK_PIN_NO(121) | 6)
#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define PINMUX_GPIO122__FUNC_KCOL0 (MTK_PIN_NO(122) | 1)
#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define PINMUX_GPIO123__FUNC_KCOL1 (MTK_PIN_NO(123) | 1)
#define PINMUX_GPIO123__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2)
#define PINMUX_GPIO123__FUNC_I2S2_DI_2 (MTK_PIN_NO(123) | 3)
#define PINMUX_GPIO123__FUNC_PWM5 (MTK_PIN_NO(123) | 4)
#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define PINMUX_GPIO124__FUNC_KCOL2 (MTK_PIN_NO(124) | 1)
#define PINMUX_GPIO124__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2)
#define PINMUX_GPIO124__FUNC_I2S1_DO_2 (MTK_PIN_NO(124) | 3)
#define PINMUX_GPIO124__FUNC_USB_DRVVBUS (MTK_PIN_NO(124) | 4)
#define PINMUX_GPIO124__FUNC_SPI_MI_2 (MTK_PIN_NO(124) | 5)
#define PINMUX_GPIO124__FUNC_PWM3 (MTK_PIN_NO(124) | 6)
#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define PINMUX_GPIO125__FUNC_SDA1 (MTK_PIN_NO(125) | 1)
#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define PINMUX_GPIO126__FUNC_SCL1 (MTK_PIN_NO(126) | 1)
#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
#define PINMUX_GPIO127__FUNC_MD_EINT1 (MTK_PIN_NO(127) | 1)
#define PINMUX_GPIO127__FUNC_DISP_PWM1 (MTK_PIN_NO(127) | 2)
#define PINMUX_GPIO127__FUNC_SPI_MO_2 (MTK_PIN_NO(127) | 3)
#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
#define PINMUX_GPIO128__FUNC_MD_EINT2 (MTK_PIN_NO(128) | 1)
#define PINMUX_GPIO128__FUNC_DSI1_TE (MTK_PIN_NO(128) | 2)
#define PINMUX_GPIO128__FUNC_SPI_CS_2 (MTK_PIN_NO(128) | 3)
#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
#define PINMUX_GPIO129__FUNC_I2S3_WS (MTK_PIN_NO(129) | 1)
#define PINMUX_GPIO129__FUNC_I2S2_WS (MTK_PIN_NO(129) | 2)
#define PINMUX_GPIO129__FUNC_PWM0 (MTK_PIN_NO(129) | 3)
#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
#define PINMUX_GPIO130__FUNC_I2S3_BCK (MTK_PIN_NO(130) | 1)
#define PINMUX_GPIO130__FUNC_I2S2_BCK (MTK_PIN_NO(130) | 2)
#define PINMUX_GPIO130__FUNC_PWM1 (MTK_PIN_NO(130) | 3)
#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
#define PINMUX_GPIO131__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 1)
#define PINMUX_GPIO131__FUNC_I2S2_MCK (MTK_PIN_NO(131) | 2)
#define PINMUX_GPIO131__FUNC_PWM2 (MTK_PIN_NO(131) | 3)
#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
#define PINMUX_GPIO132__FUNC_I2S3_DO_1 (MTK_PIN_NO(132) | 1)
#define PINMUX_GPIO132__FUNC_I2S2_DI_1 (MTK_PIN_NO(132) | 2)
#define PINMUX_GPIO132__FUNC_PWM3 (MTK_PIN_NO(132) | 3)
#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
#define PINMUX_GPIO133__FUNC_I2S3_DO_2 (MTK_PIN_NO(133) | 1)
#define PINMUX_GPIO133__FUNC_I2S2_DI_2 (MTK_PIN_NO(133) | 2)
#define PINMUX_GPIO133__FUNC_PWM4 (MTK_PIN_NO(133) | 3)
#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
#define PINMUX_GPIO134__FUNC_I2S3_DO_3 (MTK_PIN_NO(134) | 1)
#define PINMUX_GPIO134__FUNC_DISP_PWM1 (MTK_PIN_NO(134) | 2)
#define PINMUX_GPIO134__FUNC_I2S1_DO_1 (MTK_PIN_NO(134) | 3)
#define PINMUX_GPIO134__FUNC_PWM5 (MTK_PIN_NO(134) | 4)
#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
#define PINMUX_GPIO135__FUNC_I2S3_DO_4 (MTK_PIN_NO(135) | 1)
#define PINMUX_GPIO135__FUNC_DSI1_TE (MTK_PIN_NO(135) | 2)
#define PINMUX_GPIO135__FUNC_I2S1_DO_2 (MTK_PIN_NO(135) | 3)
#define PINMUX_GPIO135__FUNC_PWM6 (MTK_PIN_NO(135) | 4)
#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
#define PINMUX_GPIO136__FUNC_SDA3 (MTK_PIN_NO(136) | 1)
#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
#define PINMUX_GPIO137__FUNC_SCL3 (MTK_PIN_NO(137) | 1)
#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
#define PINMUX_GPIO138__FUNC_DPI_CK (MTK_PIN_NO(138) | 1)
#define PINMUX_GPIO138__FUNC_NLD6 (MTK_PIN_NO(138) | 2)
#define PINMUX_GPIO138__FUNC_UTXD0 (MTK_PIN_NO(138) | 3)
#define PINMUX_GPIO138__FUNC_USB_DRVVBUS (MTK_PIN_NO(138) | 4)
#define PINMUX_GPIO138__FUNC_IRDA_PDN (MTK_PIN_NO(138) | 5)
#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
#define PINMUX_GPIO139__FUNC_DPI_DE (MTK_PIN_NO(139) | 1)
#define PINMUX_GPIO139__FUNC_NLD7 (MTK_PIN_NO(139) | 2)
#define PINMUX_GPIO139__FUNC_URXD0 (MTK_PIN_NO(139) | 3)
#define PINMUX_GPIO139__FUNC_MD_UTXD (MTK_PIN_NO(139) | 4)
#define PINMUX_GPIO139__FUNC_IRDA_RXD (MTK_PIN_NO(139) | 5)
#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
#define PINMUX_GPIO140__FUNC_DPI_D0 (MTK_PIN_NO(140) | 1)
#define PINMUX_GPIO140__FUNC_NREB (MTK_PIN_NO(140) | 2)
#define PINMUX_GPIO140__FUNC_UCTS0 (MTK_PIN_NO(140) | 3)
#define PINMUX_GPIO140__FUNC_MD_URXD (MTK_PIN_NO(140) | 4)
#define PINMUX_GPIO140__FUNC_IRDA_TXD (MTK_PIN_NO(140) | 5)
#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
#define PINMUX_GPIO141__FUNC_DPI_D1 (MTK_PIN_NO(141) | 1)
#define PINMUX_GPIO141__FUNC_NRNB0 (MTK_PIN_NO(141) | 2)
#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 3)
#define PINMUX_GPIO141__FUNC_LTE_UTXD (MTK_PIN_NO(141) | 4)
#define PINMUX_GPIO141__FUNC_I2S2_WS (MTK_PIN_NO(141) | 5)
#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
#define PINMUX_GPIO142__FUNC_DPI_D2 (MTK_PIN_NO(142) | 1)
#define PINMUX_GPIO142__FUNC_NWEB (MTK_PIN_NO(142) | 2)
#define PINMUX_GPIO142__FUNC_UTXD1 (MTK_PIN_NO(142) | 3)
#define PINMUX_GPIO142__FUNC_LTE_URXD (MTK_PIN_NO(142) | 4)
#define PINMUX_GPIO142__FUNC_I2S2_BCK (MTK_PIN_NO(142) | 5)
#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
#define PINMUX_GPIO143__FUNC_DPI_D3 (MTK_PIN_NO(143) | 1)
#define PINMUX_GPIO143__FUNC_NCEB0 (MTK_PIN_NO(143) | 2)
#define PINMUX_GPIO143__FUNC_URXD1 (MTK_PIN_NO(143) | 3)
#define PINMUX_GPIO143__FUNC_TDD_TXD (MTK_PIN_NO(143) | 4)
#define PINMUX_GPIO143__FUNC_I2S2_MCK (MTK_PIN_NO(143) | 5)
#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
#define PINMUX_GPIO144__FUNC_DPI_D4 (MTK_PIN_NO(144) | 1)
#define PINMUX_GPIO144__FUNC_NALE (MTK_PIN_NO(144) | 2)
#define PINMUX_GPIO144__FUNC_UCTS1 (MTK_PIN_NO(144) | 3)
#define PINMUX_GPIO144__FUNC_TDD_TMS (MTK_PIN_NO(144) | 4)
#define PINMUX_GPIO144__FUNC_I2S2_DI_1 (MTK_PIN_NO(144) | 5)
#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
#define PINMUX_GPIO145__FUNC_DPI_D5 (MTK_PIN_NO(145) | 1)
#define PINMUX_GPIO145__FUNC_NCLE (MTK_PIN_NO(145) | 2)
#define PINMUX_GPIO145__FUNC_URTS1 (MTK_PIN_NO(145) | 3)
#define PINMUX_GPIO145__FUNC_TDD_TCK (MTK_PIN_NO(145) | 4)
#define PINMUX_GPIO145__FUNC_I2S2_DI_2 (MTK_PIN_NO(145) | 5)
#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
#define PINMUX_GPIO146__FUNC_DPI_D6 (MTK_PIN_NO(146) | 1)
#define PINMUX_GPIO146__FUNC_NLD8 (MTK_PIN_NO(146) | 2)
#define PINMUX_GPIO146__FUNC_UTXD2 (MTK_PIN_NO(146) | 3)
#define PINMUX_GPIO146__FUNC_TDD_TDI (MTK_PIN_NO(146) | 4)
#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
#define PINMUX_GPIO147__FUNC_DPI_D7 (MTK_PIN_NO(147) | 1)
#define PINMUX_GPIO147__FUNC_NLD9 (MTK_PIN_NO(147) | 2)
#define PINMUX_GPIO147__FUNC_URXD2 (MTK_PIN_NO(147) | 3)
#define PINMUX_GPIO147__FUNC_TDD_TDO (MTK_PIN_NO(147) | 4)
#define PINMUX_GPIO147__FUNC_I2S1_WS (MTK_PIN_NO(147) | 5)
#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
#define PINMUX_GPIO148__FUNC_DPI_D8 (MTK_PIN_NO(148) | 1)
#define PINMUX_GPIO148__FUNC_NLD10 (MTK_PIN_NO(148) | 2)
#define PINMUX_GPIO148__FUNC_UCTS2 (MTK_PIN_NO(148) | 3)
#define PINMUX_GPIO148__FUNC_TDD_TRSTN (MTK_PIN_NO(148) | 4)
#define PINMUX_GPIO148__FUNC_I2S1_BCK (MTK_PIN_NO(148) | 5)
#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
#define PINMUX_GPIO149__FUNC_DPI_D9 (MTK_PIN_NO(149) | 1)
#define PINMUX_GPIO149__FUNC_NLD11 (MTK_PIN_NO(149) | 2)
#define PINMUX_GPIO149__FUNC_URTS2 (MTK_PIN_NO(149) | 3)
#define PINMUX_GPIO149__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(149) | 4)
#define PINMUX_GPIO149__FUNC_I2S1_MCK (MTK_PIN_NO(149) | 5)
#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
#define PINMUX_GPIO150__FUNC_DPI_D10 (MTK_PIN_NO(150) | 1)
#define PINMUX_GPIO150__FUNC_NLD12 (MTK_PIN_NO(150) | 2)
#define PINMUX_GPIO150__FUNC_UTXD3 (MTK_PIN_NO(150) | 3)
#define PINMUX_GPIO150__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(150) | 4)
#define PINMUX_GPIO150__FUNC_I2S1_DO_1 (MTK_PIN_NO(150) | 5)
#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
#define PINMUX_GPIO151__FUNC_DPI_D11 (MTK_PIN_NO(151) | 1)
#define PINMUX_GPIO151__FUNC_NLD13 (MTK_PIN_NO(151) | 2)
#define PINMUX_GPIO151__FUNC_URXD3 (MTK_PIN_NO(151) | 3)
#define PINMUX_GPIO151__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(151) | 4)
#define PINMUX_GPIO151__FUNC_I2S1_DO_2 (MTK_PIN_NO(151) | 5)
#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
#define PINMUX_GPIO152__FUNC_DPI_HSYNC (MTK_PIN_NO(152) | 1)
#define PINMUX_GPIO152__FUNC_NLD14 (MTK_PIN_NO(152) | 2)
#define PINMUX_GPIO152__FUNC_UCTS3 (MTK_PIN_NO(152) | 3)
#define PINMUX_GPIO152__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(152) | 4)
#define PINMUX_GPIO152__FUNC_DSI1_TE (MTK_PIN_NO(152) | 5)
#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
#define PINMUX_GPIO153__FUNC_DPI_VSYNC (MTK_PIN_NO(153) | 1)
#define PINMUX_GPIO153__FUNC_NLD15 (MTK_PIN_NO(153) | 2)
#define PINMUX_GPIO153__FUNC_URTS3 (MTK_PIN_NO(153) | 3)
#define PINMUX_GPIO153__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(153) | 4)
#define PINMUX_GPIO153__FUNC_DISP_PWM1 (MTK_PIN_NO(153) | 5)
#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
#define PINMUX_GPIO154__FUNC_MSDC0_DAT0 (MTK_PIN_NO(154) | 1)
#define PINMUX_GPIO154__FUNC_NLD8 (MTK_PIN_NO(154) | 2)
#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
#define PINMUX_GPIO155__FUNC_MSDC0_DAT1 (MTK_PIN_NO(155) | 1)
#define PINMUX_GPIO155__FUNC_NLD9 (MTK_PIN_NO(155) | 2)
#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
#define PINMUX_GPIO156__FUNC_MSDC0_DAT2 (MTK_PIN_NO(156) | 1)
#define PINMUX_GPIO156__FUNC_NLD10 (MTK_PIN_NO(156) | 2)
#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
#define PINMUX_GPIO157__FUNC_MSDC0_DAT3 (MTK_PIN_NO(157) | 1)
#define PINMUX_GPIO157__FUNC_NLD11 (MTK_PIN_NO(157) | 2)
#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
#define PINMUX_GPIO158__FUNC_MSDC0_DAT4 (MTK_PIN_NO(158) | 1)
#define PINMUX_GPIO158__FUNC_NLD12 (MTK_PIN_NO(158) | 2)
#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
#define PINMUX_GPIO159__FUNC_MSDC0_DAT5 (MTK_PIN_NO(159) | 1)
#define PINMUX_GPIO159__FUNC_NLD13 (MTK_PIN_NO(159) | 2)
#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
#define PINMUX_GPIO160__FUNC_MSDC0_DAT6 (MTK_PIN_NO(160) | 1)
#define PINMUX_GPIO160__FUNC_NLD14 (MTK_PIN_NO(160) | 2)
#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
#define PINMUX_GPIO161__FUNC_MSDC0_DAT7 (MTK_PIN_NO(161) | 1)
#define PINMUX_GPIO161__FUNC_NLD15 (MTK_PIN_NO(161) | 2)
#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
#define PINMUX_GPIO162__FUNC_MSDC0_CMD (MTK_PIN_NO(162) | 1)
#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
#define PINMUX_GPIO163__FUNC_MSDC0_CLK (MTK_PIN_NO(163) | 1)
#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
#define PINMUX_GPIO164__FUNC_MSDC0_DSL (MTK_PIN_NO(164) | 1)
#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
#define PINMUX_GPIO165__FUNC_MSDC0_RSTB (MTK_PIN_NO(165) | 1)
#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
#define PINMUX_GPIO166__FUNC_SPI_CK_0 (MTK_PIN_NO(166) | 1)
#define PINMUX_GPIO166__FUNC_PWM0 (MTK_PIN_NO(166) | 3)
#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
#define PINMUX_GPIO167__FUNC_SPI_MI_0 (MTK_PIN_NO(167) | 1)
#define PINMUX_GPIO167__FUNC_PWM1 (MTK_PIN_NO(167) | 3)
#define PINMUX_GPIO167__FUNC_SPI_MO_0 (MTK_PIN_NO(167) | 4)
#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
#define PINMUX_GPIO168__FUNC_SPI_MO_0 (MTK_PIN_NO(168) | 1)
#define PINMUX_GPIO168__FUNC_MD_EINT3 (MTK_PIN_NO(168) | 2)
#define PINMUX_GPIO168__FUNC_PWM2 (MTK_PIN_NO(168) | 3)
#define PINMUX_GPIO168__FUNC_SPI_MI_0 (MTK_PIN_NO(168) | 4)
#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
#define PINMUX_GPIO169__FUNC_SPI_CS_0 (MTK_PIN_NO(169) | 1)
#define PINMUX_GPIO169__FUNC_MD_EINT4 (MTK_PIN_NO(169) | 2)
#define PINMUX_GPIO169__FUNC_PWM3 (MTK_PIN_NO(169) | 3)
#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
#define PINMUX_GPIO170__FUNC_MSDC1_CMD (MTK_PIN_NO(170) | 1)
#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
#define PINMUX_GPIO171__FUNC_MSDC1_DAT0 (MTK_PIN_NO(171) | 1)
#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
#define PINMUX_GPIO172__FUNC_MSDC1_DAT1 (MTK_PIN_NO(172) | 1)
#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
#define PINMUX_GPIO173__FUNC_MSDC1_DAT2 (MTK_PIN_NO(173) | 1)
#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
#define PINMUX_GPIO174__FUNC_MSDC1_DAT3 (MTK_PIN_NO(174) | 1)
#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
#define PINMUX_GPIO175__FUNC_MSDC1_CLK (MTK_PIN_NO(175) | 1)
#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
#define PINMUX_GPIO176__FUNC_PWRAP_SPIMI (MTK_PIN_NO(176) | 1)
#define PINMUX_GPIO176__FUNC_PWRAP_SPIMO (MTK_PIN_NO(176) | 2)
#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
#define PINMUX_GPIO177__FUNC_PWRAP_SPIMO (MTK_PIN_NO(177) | 1)
#define PINMUX_GPIO177__FUNC_PWRAP_SPIMI (MTK_PIN_NO(177) | 2)
#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
#define PINMUX_GPIO178__FUNC_PWRAP_SPICK (MTK_PIN_NO(178) | 1)
#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
#define PINMUX_GPIO179__FUNC_PWRAP_SPICS (MTK_PIN_NO(179) | 1)
#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
#define PINMUX_GPIO180__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(180) | 1)
#define PINMUX_GPIO180__FUNC_I2S1_WS (MTK_PIN_NO(180) | 2)
#define PINMUX_GPIO180__FUNC_I2S2_WS (MTK_PIN_NO(180) | 3)
#define PINMUX_GPIO180__FUNC_I2S0_WS (MTK_PIN_NO(180) | 4)
#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
#define PINMUX_GPIO181__FUNC_AUD_DAT_MISO_1 (MTK_PIN_NO(181) | 1)
#define PINMUX_GPIO181__FUNC_I2S1_BCK (MTK_PIN_NO(181) | 2)
#define PINMUX_GPIO181__FUNC_I2S2_BCK (MTK_PIN_NO(181) | 3)
#define PINMUX_GPIO181__FUNC_I2S0_BCK (MTK_PIN_NO(181) | 4)
#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
#define PINMUX_GPIO182__FUNC_AUD_DAT_MOSI_1 (MTK_PIN_NO(182) | 1)
#define PINMUX_GPIO182__FUNC_I2S1_MCK (MTK_PIN_NO(182) | 2)
#define PINMUX_GPIO182__FUNC_I2S2_MCK (MTK_PIN_NO(182) | 3)
#define PINMUX_GPIO182__FUNC_I2S0_MCK (MTK_PIN_NO(182) | 4)
#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
#define PINMUX_GPIO183__FUNC_AUD_DAT_MISO_2 (MTK_PIN_NO(183) | 1)
#define PINMUX_GPIO183__FUNC_I2S1_DO_1 (MTK_PIN_NO(183) | 2)
#define PINMUX_GPIO183__FUNC_I2S2_DI_1 (MTK_PIN_NO(183) | 3)
#define PINMUX_GPIO183__FUNC_I2S0_DO (MTK_PIN_NO(183) | 4)
#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
#define PINMUX_GPIO184__FUNC_AUD_DAT_MOSI_2 (MTK_PIN_NO(184) | 1)
#define PINMUX_GPIO184__FUNC_I2S1_DO_2 (MTK_PIN_NO(184) | 2)
#define PINMUX_GPIO184__FUNC_I2S2_DI_2 (MTK_PIN_NO(184) | 3)
#define PINMUX_GPIO184__FUNC_I2S0_DI (MTK_PIN_NO(184) | 4)
#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
#define PINMUX_GPIO185__FUNC_RTC32K_CK (MTK_PIN_NO(185) | 1)
#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
#define PINMUX_GPIO186__FUNC_DISP_PWM0 (MTK_PIN_NO(186) | 1)
#define PINMUX_GPIO186__FUNC_DISP_PWM1 (MTK_PIN_NO(186) | 2)
#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
#define PINMUX_GPIO187__FUNC_SRCLKENAI (MTK_PIN_NO(187) | 1)
#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
#define PINMUX_GPIO188__FUNC_SRCLKENAI2 (MTK_PIN_NO(188) | 1)
#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
#define PINMUX_GPIO189__FUNC_SRCLKENA0 (MTK_PIN_NO(189) | 1)
#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
#define PINMUX_GPIO190__FUNC_SRCLKENA1 (MTK_PIN_NO(190) | 1)
#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
#define PINMUX_GPIO191__FUNC_WATCHDOG_AO (MTK_PIN_NO(191) | 1)
#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
#define PINMUX_GPIO192__FUNC_I2S0_WS (MTK_PIN_NO(192) | 1)
#define PINMUX_GPIO192__FUNC_I2S1_WS (MTK_PIN_NO(192) | 2)
#define PINMUX_GPIO192__FUNC_I2S2_WS (MTK_PIN_NO(192) | 3)
#define PINMUX_GPIO192__FUNC_NCEB1 (MTK_PIN_NO(192) | 4)
#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
#define PINMUX_GPIO193__FUNC_I2S0_BCK (MTK_PIN_NO(193) | 1)
#define PINMUX_GPIO193__FUNC_I2S1_BCK (MTK_PIN_NO(193) | 2)
#define PINMUX_GPIO193__FUNC_I2S2_BCK (MTK_PIN_NO(193) | 3)
#define PINMUX_GPIO193__FUNC_NRNB1 (MTK_PIN_NO(193) | 4)
#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
#define PINMUX_GPIO194__FUNC_I2S0_MCK (MTK_PIN_NO(194) | 1)
#define PINMUX_GPIO194__FUNC_I2S1_MCK (MTK_PIN_NO(194) | 2)
#define PINMUX_GPIO194__FUNC_I2S2_MCK (MTK_PIN_NO(194) | 3)
#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
#define PINMUX_GPIO195__FUNC_I2S0_DO (MTK_PIN_NO(195) | 1)
#define PINMUX_GPIO195__FUNC_I2S1_DO_1 (MTK_PIN_NO(195) | 2)
#define PINMUX_GPIO195__FUNC_I2S2_DI_1 (MTK_PIN_NO(195) | 3)
#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
#define PINMUX_GPIO196__FUNC_I2S0_DI (MTK_PIN_NO(196) | 1)
#define PINMUX_GPIO196__FUNC_I2S1_DO_2 (MTK_PIN_NO(196) | 2)
#define PINMUX_GPIO196__FUNC_I2S2_DI_2 (MTK_PIN_NO(196) | 3)
#endif

18
include/dt-bindings/power/imx8mp-power.h
View file

@ -32,4 +32,22 @@
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
#define IMX8MP_MEDIABLK_PD_ISP 6
#define IMX8MP_MEDIABLK_PD_DWE 7
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
#define IMX8MP_HDMIBLK_PD_LCDIF 1
#define IMX8MP_HDMIBLK_PD_PAI 2
#define IMX8MP_HDMIBLK_PD_PVI 3
#define IMX8MP_HDMIBLK_PD_TRNG 4
#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
#endif

26
include/dt-bindings/power/qcom-rpmpd.h
View file

@ -20,6 +20,14 @@
#define SDX55_MX 1
#define SDX55_CX 2
/* SDX65 Power Domain Indexes */
#define SDX65_MSS 0
#define SDX65_MX 1
#define SDX65_MX_AO 2
#define SDX65_CX 3
#define SDX65_CX_AO 4
#define SDX65_MXC 5
/* SM6350 Power Domain Indexes */
#define SM6350_CX 0
#define SM6350_GFX 1
@ -117,6 +125,24 @@
#define SC8180X_MX 9
#define SC8180X_MX_AO 10
/* SC8280XP Power Domain Indexes */
#define SC8280XP_CX 0
#define SC8280XP_CX_AO 1
#define SC8280XP_DDR 2
#define SC8280XP_EBI 3
#define SC8280XP_GFX 4
#define SC8280XP_LCX 5
#define SC8280XP_LMX 6
#define SC8280XP_MMCX 7
#define SC8280XP_MMCX_AO 8
#define SC8280XP_MSS 9
#define SC8280XP_MX 10
#define SC8280XP_MXC 12
#define SC8280XP_MX_AO 11
#define SC8280XP_NSP 13
#define SC8280XP_QPHY 14
#define SC8280XP_XO 15
/* SDM845 Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48

45
include/dt-bindings/power/r8a779g0-sysc.h Normal file
View file

@ -0,0 +1,45 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779G0_PD_A1E0D0C0 0
#define R8A779G0_PD_A1E0D0C1 1
#define R8A779G0_PD_A1E0D1C0 2
#define R8A779G0_PD_A1E0D1C1 3
#define R8A779G0_PD_A2E0D0 16
#define R8A779G0_PD_A2E0D1 17
#define R8A779G0_PD_A3E0 20
#define R8A779G0_PD_A33DGA 24
#define R8A779G0_PD_A23DGB 25
#define R8A779G0_PD_A1DSP0 33
#define R8A779G0_PD_A2IMP01 34
#define R8A779G0_PD_A2PSC 35
#define R8A779G0_PD_A2CV0 36
#define R8A779G0_PD_A2CV1 37
#define R8A779G0_PD_A1CNN0 41
#define R8A779G0_PD_A2CN0 42
#define R8A779G0_PD_A3IR 43
#define R8A779G0_PD_A1DSP1 45
#define R8A779G0_PD_A2IMP23 46
#define R8A779G0_PD_A2DMA 47
#define R8A779G0_PD_A2CV2 48
#define R8A779G0_PD_A2CV3 49
#define R8A779G0_PD_A1DSP2 53
#define R8A779G0_PD_A1DSP3 54
#define R8A779G0_PD_A3VIP0 56
#define R8A779G0_PD_A3VIP1 57
#define R8A779G0_PD_A3VIP2 58
#define R8A779G0_PD_A3ISP0 60
#define R8A779G0_PD_A3ISP1 61
/* Always-on power area */
#define R8A779G0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/

125
include/dt-bindings/reset/amlogic,meson-s4-reset.h Normal file
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@ -0,0 +1,125 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Zelong Dong <zelong.dong@amlogic.com>
*
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
/* RESET0 */
#define RESET_USB_DDR0 0
#define RESET_USB_DDR1 1
#define RESET_USB_DDR2 2
#define RESET_USB_DDR3 3
#define RESET_USBCTRL 4
/* 5-7 */
#define RESET_USBPHY20 8
#define RESET_USBPHY21 9
/* 10-15 */
#define RESET_HDMITX_APB 16
#define RESET_BRG_VCBUS_DEC 17
#define RESET_VCBUS 18
#define RESET_VID_PLL_DIV 19
#define RESET_VDI6 20
#define RESET_GE2D 21
#define RESET_HDMITXPHY 22
#define RESET_VID_LOCK 23
#define RESET_VENCL 24
#define RESET_VDAC 25
#define RESET_VENCP 26
#define RESET_VENCI 27
#define RESET_RDMA 28
#define RESET_HDMI_TX 29
#define RESET_VIU 30
#define RESET_VENC 31
/* RESET1 */
#define RESET_AUDIO 32
#define RESET_MALI_APB 33
#define RESET_MALI 34
#define RESET_DDR_APB 35
#define RESET_DDR 36
#define RESET_DOS_APB 37
#define RESET_DOS 38
/* 39-47 */
#define RESET_ETH 48
/* 49-51 */
#define RESET_DEMOD 52
/* 53-63 */
/* RESET2 */
#define RESET_ABUS_ARB 64
#define RESET_IR_CTRL 65
#define RESET_TEMPSENSOR_DDR 66
#define RESET_TEMPSENSOR_PLL 67
/* 68-71 */
#define RESET_SMART_CARD 72
#define RESET_SPICC0 73
/* 74 */
#define RESET_RSA 75
/* 76-79 */
#define RESET_MSR_CLK 80
#define RESET_SPIFC 81
#define RESET_SARADC 82
/* 83-87 */
#define RESET_ACODEC 88
#define RESET_CEC 89
#define RESET_AFIFO 90
#define RESET_WATCHDOG 91
/* 92-95 */
/* RESET3 */
/* 96-127 */
/* RESET4 */
/* 128-131 */
#define RESET_PWM_AB 132
#define RESET_PWM_CD 133
#define RESET_PWM_EF 134
#define RESET_PWM_GH 135
#define RESET_PWM_IJ 136
/* 137 */
#define RESET_UART_A 138
#define RESET_UART_B 139
#define RESET_UART_C 140
#define RESET_UART_D 141
#define RESET_UART_E 142
/* 143 */
#define RESET_I2C_S_A 144
#define RESET_I2C_M_A 145
#define RESET_I2C_M_B 146
#define RESET_I2C_M_C 147
#define RESET_I2C_M_D 148
#define RESET_I2C_M_E 149
/* 150-151 */
#define RESET_SD_EMMC_A 152
#define RESET_SD_EMMC_B 153
#define RESET_NAND_EMMC 154
/* 155-159 */
/* RESET5 */
#define RESET_BRG_VDEC_PIPL0 160
#define RESET_BRG_HEVCF_PIPL0 161
/* 162 */
#define RESET_BRG_HCODEC_PIPL0 163
#define RESET_BRG_GE2D_PIPL0 164
#define RESET_BRG_VPU_PIPL0 165
#define RESET_BRG_CPU_PIPL0 166
#define RESET_BRG_MALI_PIPL0 167
/* 168 */
#define RESET_BRG_MALI_PIPL1 169
/* 170-171 */
#define RESET_BRG_HEVCF_PIPL1 172
#define RESET_BRG_HEVCB_PIPL1 173
/* 174-183 */
#define RESET_RAMA 184
/* 185-186 */
#define RESET_BRG_NIC_VAPB 187
#define RESET_BRG_NIC_DSU 188
#define RESET_BRG_NIC_SYSCLK 189
#define RESET_BRG_NIC_MAIN 190
#define RESET_BRG_NIC_ALL 191
#endif

55
include/dt-bindings/reset/mt7986-resets.h Normal file
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@ -0,0 +1,55 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
/* INFRACFG resets */
#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
#define MT7986_INFRACFG_SSUSB_SW_RST 7
#define MT7986_INFRACFG_EIP97_SW_RST 8
#define MT7986_INFRACFG_AUDIO_SW_RST 13
#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
#define MT7986_INFRACFG_TRNG_SW_RST 17
#define MT7986_INFRACFG_AP_DMA_SW_RST 32
#define MT7986_INFRACFG_I2C_SW_RST 33
#define MT7986_INFRACFG_NFI_SW_RST 34
#define MT7986_INFRACFG_SPI0_SW_RST 35
#define MT7986_INFRACFG_SPI1_SW_RST 36
#define MT7986_INFRACFG_UART0_SW_RST 37
#define MT7986_INFRACFG_UART1_SW_RST 38
#define MT7986_INFRACFG_UART2_SW_RST 39
#define MT7986_INFRACFG_AUXADC_SW_RST 43
#define MT7986_INFRACFG_APXGPT_SW_RST 66
#define MT7986_INFRACFG_PWM_SW_RST 68
#define MT7986_INFRACFG_SW_RST_NUM 69
/* TOPRGU resets */
#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
#define MT7986_TOPRGU_SGMII0_SW_RST 1
#define MT7986_TOPRGU_SGMII1_SW_RST 2
#define MT7986_TOPRGU_INFRA_SW_RST 3
#define MT7986_TOPRGU_U2PHY_SW_RST 5
#define MT7986_TOPRGU_PCIE_SW_RST 6
#define MT7986_TOPRGU_SSUSB_SW_RST 7
#define MT7986_TOPRGU_ETHDMA_SW_RST 20
#define MT7986_TOPRGU_CONSYS_SW_RST 23
#define MT7986_TOPRGU_SW_RST_NUM 24
/* ETHSYS Subsystem resets */
#define MT7986_ETHSYS_FE_SW_RST 6
#define MT7986_ETHSYS_PMTR_SW_RST 8
#define MT7986_ETHSYS_GMAC_SW_RST 23
#define MT7986_ETHSYS_PPE0_SW_RST 30
#define MT7986_ETHSYS_PPE1_SW_RST 31
#define MT7986_ETHSYS_SW_RST_NUM 32
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */

36
include/dt-bindings/reset/mt8186-resets.h Normal file
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@ -0,0 +1,36 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Runyang Chen <runyang.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
#define MT8186_TOPRGU_INFRA_SW_RST 0
#define MT8186_TOPRGU_MM_SW_RST 1
#define MT8186_TOPRGU_MFG_SW_RST 2
#define MT8186_TOPRGU_VENC_SW_RST 3
#define MT8186_TOPRGU_VDEC_SW_RST 4
#define MT8186_TOPRGU_IMG_SW_RST 5
#define MT8186_TOPRGU_DDR_SW_RST 6
#define MT8186_TOPRGU_INFRA_AO_SW_RST 8
#define MT8186_TOPRGU_CONNSYS_SW_RST 9
#define MT8186_TOPRGU_APMIXED_SW_RST 10
#define MT8186_TOPRGU_PWRAP_SW_RST 11
#define MT8186_TOPRGU_CONN_MCU_SW_RST 12
#define MT8186_TOPRGU_IPNNA_SW_RST 13
#define MT8186_TOPRGU_WPE_SW_RST 14
#define MT8186_TOPRGU_ADSP_SW_RST 15
#define MT8186_TOPRGU_AUDIO_SW_RST 17
#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18
#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19
#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20
#define MT8186_TOPRGU_IPE_SW_RST 21
#define MT8186_TOPRGU_IMG2_SW_RST 22
#define MT8186_TOPRGU_SW_RST_NUM 23
/* MMSYS resets */
#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */

3
include/dt-bindings/reset/mt8192-resets.h
View file

@ -27,4 +27,7 @@
#define MT8192_TOPRGU_SW_RST_NUM 23
/* MMSYS resets */
#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

24
include/dt-bindings/reset/stm32mp1-resets.h
View file

@ -107,17 +107,17 @@
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI0_SPI6 0
#define RST_SCMI0_I2C4 1
#define RST_SCMI0_I2C6 2
#define RST_SCMI0_USART1 3
#define RST_SCMI0_STGEN 4
#define RST_SCMI0_GPIOZ 5
#define RST_SCMI0_CRYP1 6
#define RST_SCMI0_HASH1 7
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
#define RST_SCMI0_MCU_HOLD_BOOT 11
#define RST_SCMI_SPI6 0
#define RST_SCMI_I2C4 1
#define RST_SCMI_I2C6 2
#define RST_SCMI_USART1 3
#define RST_SCMI_STGEN 4
#define RST_SCMI_GPIOZ 5
#define RST_SCMI_CRYP1 6
#define RST_SCMI_HASH1 7
#define RST_SCMI_RNG1 8
#define RST_SCMI_MDMA 9
#define RST_SCMI_MCU 10
#define RST_SCMI_MCU_HOLD_BOOT 11
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */

100
include/dt-bindings/reset/stm32mp13-resets.h Normal file
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@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_RESET_H_
#define _DT_BINDINGS_STM32MP13_RESET_H_
#define TIM2_R 13568
#define TIM3_R 13569
#define TIM4_R 13570
#define TIM5_R 13571
#define TIM6_R 13572
#define TIM7_R 13573
#define LPTIM1_R 13577
#define SPI2_R 13579
#define SPI3_R 13580
#define USART3_R 13583
#define UART4_R 13584
#define UART5_R 13585
#define UART7_R 13586
#define UART8_R 13587
#define I2C1_R 13589
#define I2C2_R 13590
#define SPDIF_R 13594
#define TIM1_R 13632
#define TIM8_R 13633
#define SPI1_R 13640
#define USART6_R 13645
#define SAI1_R 13648
#define SAI2_R 13649
#define DFSDM_R 13652
#define FDCAN_R 13656
#define LPTIM2_R 13696
#define LPTIM3_R 13697
#define LPTIM4_R 13698
#define LPTIM5_R 13699
#define SYSCFG_R 13707
#define VREF_R 13709
#define DTS_R 13712
#define PMBCTRL_R 13713
#define LTDC_R 13760
#define DCMIPP_R 13761
#define DDRPERFM_R 13768
#define USBPHY_R 13776
#define STGEN_R 13844
#define USART1_R 13888
#define USART2_R 13889
#define SPI4_R 13890
#define SPI5_R 13891
#define I2C3_R 13892
#define I2C4_R 13893
#define I2C5_R 13894
#define TIM12_R 13895
#define TIM13_R 13896
#define TIM14_R 13897
#define TIM15_R 13898
#define TIM16_R 13899
#define TIM17_R 13900
#define DMA1_R 13952
#define DMA2_R 13953
#define DMAMUX1_R 13954
#define DMA3_R 13955
#define DMAMUX2_R 13956
#define ADC1_R 13957
#define ADC2_R 13958
#define USBO_R 13960
#define GPIOA_R 14080
#define GPIOB_R 14081
#define GPIOC_R 14082
#define GPIOD_R 14083
#define GPIOE_R 14084
#define GPIOF_R 14085
#define GPIOG_R 14086
#define GPIOH_R 14087
#define GPIOI_R 14088
#define TSC_R 14095
#define PKA_R 14146
#define SAES_R 14147
#define CRYP1_R 14148
#define HASH1_R 14149
#define RNG1_R 14150
#define AXIMC_R 14160
#define MDMA_R 14208
#define MCE_R 14209
#define ETH1MAC_R 14218
#define FMC_R 14220
#define QSPI_R 14222
#define SDMMC1_R 14224
#define SDMMC2_R 14225
#define CRC1_R 14228
#define USBH_R 14232
#define ETH2MAC_R 14238
/* SCMI reset domain identifiers */
#define RST_SCMI_LTDC 0
#define RST_SCMI_MDMA 1
#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */

2
include/dt-bindings/reset/tegra234-reset.h
View file

@ -40,6 +40,8 @@
#define TEGRA234_RESET_PWM6 73U
#define TEGRA234_RESET_PWM7 74U
#define TEGRA234_RESET_PWM8 75U
#define TEGRA234_RESET_QSPI0 76U
#define TEGRA234_RESET_QSPI1 77U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
#define TEGRA234_RESET_PEX0_CORE_0 116U

20
include/dt-bindings/sound/cs35l45.h Normal file
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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
*
* Copyright 2022 Cirrus Logic, Inc.
*/
#ifndef DT_CS35L45_H
#define DT_CS35L45_H
/*
* cirrus,asp-sdout-hiz-ctrl
*
* TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
* TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
*/
#define CS35L45_ASP_TX_HIZ_UNUSED 0x1
#define CS35L45_ASP_TX_HIZ_DISABLED 0x2
#endif /* DT_CS35L45_H */

14
include/keys/system_keyring.h
View file

@ -10,6 +10,13 @@
#include <linux/key.h>
enum blacklist_hash_type {
/* TBSCertificate hash */
BLACKLIST_HASH_X509_TBS = 1,
/* Raw data hash */
BLACKLIST_HASH_BINARY = 2,
};
#ifdef CONFIG_SYSTEM_TRUSTED_KEYRING
extern int restrict_link_by_builtin_trusted(struct key *keyring,
@ -54,13 +61,14 @@ static inline void __init set_machine_trusted_keys(struct key *keyring)
extern struct pkcs7_message *pkcs7;
#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING
extern int mark_hash_blacklisted(const char *hash);
extern int mark_hash_blacklisted(const u8 *hash, size_t hash_len,
enum blacklist_hash_type hash_type);
extern int is_hash_blacklisted(const u8 *hash, size_t hash_len,
const char *type);
enum blacklist_hash_type hash_type);
extern int is_binary_blacklisted(const u8 *hash, size_t hash_len);
#else
static inline int is_hash_blacklisted(const u8 *hash, size_t hash_len,
const char *type)
enum blacklist_hash_type hash_type)
{
return 0;
}

2
include/keys/trusted-type.h
View file

@ -64,7 +64,7 @@ struct trusted_key_ops {
/* Unseal a key. */
int (*unseal)(struct trusted_key_payload *p, char *datablob);
/* Get a randomized key. */
/* Optional: Get a randomized key. */
int (*get_random)(unsigned char *key, size_t key_len);
/* Exit key interface. */

11
include/keys/trusted_caam.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2021 Pengutronix, Ahmad Fatoum <kernel@pengutronix.de>
*/
#ifndef __CAAM_TRUSTED_KEY_H
#define __CAAM_TRUSTED_KEY_H
extern struct trusted_key_ops trusted_key_caam_ops;
#endif

406
include/kunit/resource.h Normal file
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@ -0,0 +1,406 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* KUnit resource API for test managed resources (allocations, etc.).
*
* Copyright (C) 2022, Google LLC.
* Author: Daniel Latypov <dlatypov@google.com>
*/
#ifndef _KUNIT_RESOURCE_H
#define _KUNIT_RESOURCE_H
#include <kunit/test.h>
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
struct kunit_resource;
typedef int (*kunit_resource_init_t)(struct kunit_resource *, void *);
typedef void (*kunit_resource_free_t)(struct kunit_resource *);
/**
* struct kunit_resource - represents a *test managed resource*
* @data: for the user to store arbitrary data.
* @name: optional name
* @free: a user supplied function to free the resource.
*
* Represents a *test managed resource*, a resource which will automatically be
* cleaned up at the end of a test case. This cleanup is performed by the 'free'
* function. The struct kunit_resource itself is freed automatically with
* kfree() if it was allocated by KUnit (e.g., by kunit_alloc_resource()), but
* must be freed by the user otherwise.
*
* Resources are reference counted so if a resource is retrieved via
* kunit_alloc_and_get_resource() or kunit_find_resource(), we need
* to call kunit_put_resource() to reduce the resource reference count
* when finished with it. Note that kunit_alloc_resource() does not require a
* kunit_resource_put() because it does not retrieve the resource itself.
*
* Example:
*
* .. code-block:: c
*
* struct kunit_kmalloc_params {
* size_t size;
* gfp_t gfp;
* };
*
* static int kunit_kmalloc_init(struct kunit_resource *res, void *context)
* {
* struct kunit_kmalloc_params *params = context;
* res->data = kmalloc(params->size, params->gfp);
*
* if (!res->data)
* return -ENOMEM;
*
* return 0;
* }
*
* static void kunit_kmalloc_free(struct kunit_resource *res)
* {
* kfree(res->data);
* }
*
* void *kunit_kmalloc(struct kunit *test, size_t size, gfp_t gfp)
* {
* struct kunit_kmalloc_params params;
*
* params.size = size;
* params.gfp = gfp;
*
* return kunit_alloc_resource(test, kunit_kmalloc_init,
* kunit_kmalloc_free, &params);
* }
*
* Resources can also be named, with lookup/removal done on a name
* basis also. kunit_add_named_resource(), kunit_find_named_resource()
* and kunit_destroy_named_resource(). Resource names must be
* unique within the test instance.
*/
struct kunit_resource {
void *data;
const char *name;
kunit_resource_free_t free;
/* private: internal use only. */
struct kref refcount;
struct list_head node;
bool should_kfree;
};
/**
* kunit_get_resource() - Hold resource for use. Should not need to be used
* by most users as we automatically get resources
* retrieved by kunit_find_resource*().
* @res: resource
*/
static inline void kunit_get_resource(struct kunit_resource *res)
{
kref_get(&res->refcount);
}
/*
* Called when refcount reaches zero via kunit_put_resource();
* should not be called directly.
*/
static inline void kunit_release_resource(struct kref *kref)
{
struct kunit_resource *res = container_of(kref, struct kunit_resource,
refcount);
if (res->free)
res->free(res);
/* 'res' is valid here, as if should_kfree is set, res->free may not free
* 'res' itself, just res->data
*/
if (res->should_kfree)
kfree(res);
}
/**
* kunit_put_resource() - When caller is done with retrieved resource,
* kunit_put_resource() should be called to drop
* reference count. The resource list maintains
* a reference count on resources, so if no users
* are utilizing a resource and it is removed from
* the resource list, it will be freed via the
* associated free function (if any). Only
* needs to be used if we alloc_and_get() or
* find() resource.
* @res: resource
*/
static inline void kunit_put_resource(struct kunit_resource *res)
{
kref_put(&res->refcount, kunit_release_resource);
}
/**
* __kunit_add_resource() - Internal helper to add a resource.
*
* res->should_kfree is not initialised.
* @test: The test context object.
* @init: a user-supplied function to initialize the result (if needed). If
* none is supplied, the resource data value is simply set to @data.
* If an init function is supplied, @data is passed to it instead.
* @free: a user-supplied function to free the resource (if needed).
* @res: The resource.
* @data: value to pass to init function or set in resource data field.
*/
int __kunit_add_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
struct kunit_resource *res,
void *data);
/**
* kunit_add_resource() - Add a *test managed resource*.
* @test: The test context object.
* @init: a user-supplied function to initialize the result (if needed). If
* none is supplied, the resource data value is simply set to @data.
* If an init function is supplied, @data is passed to it instead.
* @free: a user-supplied function to free the resource (if needed).
* @res: The resource.
* @data: value to pass to init function or set in resource data field.
*/
static inline int kunit_add_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
struct kunit_resource *res,
void *data)
{
res->should_kfree = false;
return __kunit_add_resource(test, init, free, res, data);
}
static inline struct kunit_resource *
kunit_find_named_resource(struct kunit *test, const char *name);
/**
* kunit_add_named_resource() - Add a named *test managed resource*.
* @test: The test context object.
* @init: a user-supplied function to initialize the resource data, if needed.
* @free: a user-supplied function to free the resource data, if needed.
* @res: The resource.
* @name: name to be set for resource.
* @data: value to pass to init function or set in resource data field.
*/
static inline int kunit_add_named_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
struct kunit_resource *res,
const char *name,
void *data)
{
struct kunit_resource *existing;
if (!name)
return -EINVAL;
existing = kunit_find_named_resource(test, name);
if (existing) {
kunit_put_resource(existing);
return -EEXIST;
}
res->name = name;
res->should_kfree = false;
return __kunit_add_resource(test, init, free, res, data);
}
/**
* kunit_alloc_and_get_resource() - Allocates and returns a *test managed resource*.
* @test: The test context object.
* @init: a user supplied function to initialize the resource.
* @free: a user supplied function to free the resource (if needed).
* @internal_gfp: gfp to use for internal allocations, if unsure, use GFP_KERNEL
* @context: for the user to pass in arbitrary data to the init function.
*
* Allocates a *test managed resource*, a resource which will automatically be
* cleaned up at the end of a test case. See &struct kunit_resource for an
* example.
*
* This is effectively identical to kunit_alloc_resource, but returns the
* struct kunit_resource pointer, not just the 'data' pointer. It therefore
* also increments the resource's refcount, so kunit_put_resource() should be
* called when you've finished with it.
*
* Note: KUnit needs to allocate memory for a kunit_resource object. You must
* specify an @internal_gfp that is compatible with the use context of your
* resource.
*/
static inline struct kunit_resource *
kunit_alloc_and_get_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
gfp_t internal_gfp,
void *context)
{
struct kunit_resource *res;
int ret;
res = kzalloc(sizeof(*res), internal_gfp);
if (!res)
return NULL;
res->should_kfree = true;
ret = __kunit_add_resource(test, init, free, res, context);
if (!ret) {
/*
* bump refcount for get; kunit_resource_put() should be called
* when done.
*/
kunit_get_resource(res);
return res;
}
return NULL;
}
/**
* kunit_alloc_resource() - Allocates a *test managed resource*.
* @test: The test context object.
* @init: a user supplied function to initialize the resource.
* @free: a user supplied function to free the resource (if needed).
* @internal_gfp: gfp to use for internal allocations, if unsure, use GFP_KERNEL
* @context: for the user to pass in arbitrary data to the init function.
*
* Allocates a *test managed resource*, a resource which will automatically be
* cleaned up at the end of a test case. See &struct kunit_resource for an
* example.
*
* Note: KUnit needs to allocate memory for a kunit_resource object. You must
* specify an @internal_gfp that is compatible with the use context of your
* resource.
*/
static inline void *kunit_alloc_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
gfp_t internal_gfp,
void *context)
{
struct kunit_resource *res;
res = kzalloc(sizeof(*res), internal_gfp);
if (!res)
return NULL;
res->should_kfree = true;
if (!__kunit_add_resource(test, init, free, res, context))
return res->data;
return NULL;
}
typedef bool (*kunit_resource_match_t)(struct kunit *test,
struct kunit_resource *res,
void *match_data);
/**
* kunit_resource_instance_match() - Match a resource with the same instance.
* @test: Test case to which the resource belongs.
* @res: The resource.
* @match_data: The resource pointer to match against.
*
* An instance of kunit_resource_match_t that matches a resource whose
* allocation matches @match_data.
*/
static inline bool kunit_resource_instance_match(struct kunit *test,
struct kunit_resource *res,
void *match_data)
{
return res->data == match_data;
}
/**
* kunit_resource_name_match() - Match a resource with the same name.
* @test: Test case to which the resource belongs.
* @res: The resource.
* @match_name: The name to match against.
*/
static inline bool kunit_resource_name_match(struct kunit *test,
struct kunit_resource *res,
void *match_name)
{
return res->name && strcmp(res->name, match_name) == 0;
}
/**
* kunit_find_resource() - Find a resource using match function/data.
* @test: Test case to which the resource belongs.
* @match: match function to be applied to resources/match data.
* @match_data: data to be used in matching.
*/
static inline struct kunit_resource *
kunit_find_resource(struct kunit *test,
kunit_resource_match_t match,
void *match_data)
{
struct kunit_resource *res, *found = NULL;
unsigned long flags;
spin_lock_irqsave(&test->lock, flags);
list_for_each_entry_reverse(res, &test->resources, node) {
if (match(test, res, (void *)match_data)) {
found = res;
kunit_get_resource(found);
break;
}
}
spin_unlock_irqrestore(&test->lock, flags);
return found;
}
/**
* kunit_find_named_resource() - Find a resource using match name.
* @test: Test case to which the resource belongs.
* @name: match name.
*/
static inline struct kunit_resource *
kunit_find_named_resource(struct kunit *test,
const char *name)
{
return kunit_find_resource(test, kunit_resource_name_match,
(void *)name);
}
/**
* kunit_destroy_resource() - Find a kunit_resource and destroy it.
* @test: Test case to which the resource belongs.
* @match: Match function. Returns whether a given resource matches @match_data.
* @match_data: Data passed into @match.
*
* RETURNS:
* 0 if kunit_resource is found and freed, -ENOENT if not found.
*/
int kunit_destroy_resource(struct kunit *test,
kunit_resource_match_t match,
void *match_data);
static inline int kunit_destroy_named_resource(struct kunit *test,
const char *name)
{
return kunit_destroy_resource(test, kunit_resource_name_match,
(void *)name);
}
/**
* kunit_remove_resource() - remove resource from resource list associated with
* test.
* @test: The test context object.
* @res: The resource to be removed.
*
* Note that the resource will not be immediately freed since it is likely
* the caller has a reference to it via alloc_and_get() or find();
* in this case a final call to kunit_put_resource() is required.
*/
void kunit_remove_resource(struct kunit *test, struct kunit_resource *res);
#endif /* _KUNIT_RESOURCE_H */

422
include/kunit/test.h
View file

@ -27,78 +27,6 @@
#include <asm/rwonce.h>
struct kunit_resource;
typedef int (*kunit_resource_init_t)(struct kunit_resource *, void *);
typedef void (*kunit_resource_free_t)(struct kunit_resource *);
/**
* struct kunit_resource - represents a *test managed resource*
* @data: for the user to store arbitrary data.
* @name: optional name
* @free: a user supplied function to free the resource. Populated by
* kunit_resource_alloc().
*
* Represents a *test managed resource*, a resource which will automatically be
* cleaned up at the end of a test case.
*
* Resources are reference counted so if a resource is retrieved via
* kunit_alloc_and_get_resource() or kunit_find_resource(), we need
* to call kunit_put_resource() to reduce the resource reference count
* when finished with it. Note that kunit_alloc_resource() does not require a
* kunit_resource_put() because it does not retrieve the resource itself.
*
* Example:
*
* .. code-block:: c
*
* struct kunit_kmalloc_params {
* size_t size;
* gfp_t gfp;
* };
*
* static int kunit_kmalloc_init(struct kunit_resource *res, void *context)
* {
* struct kunit_kmalloc_params *params = context;
* res->data = kmalloc(params->size, params->gfp);
*
* if (!res->data)
* return -ENOMEM;
*
* return 0;
* }
*
* static void kunit_kmalloc_free(struct kunit_resource *res)
* {
* kfree(res->data);
* }
*
* void *kunit_kmalloc(struct kunit *test, size_t size, gfp_t gfp)
* {
* struct kunit_kmalloc_params params;
*
* params.size = size;
* params.gfp = gfp;
*
* return kunit_alloc_resource(test, kunit_kmalloc_init,
* kunit_kmalloc_free, &params);
* }
*
* Resources can also be named, with lookup/removal done on a name
* basis also. kunit_add_named_resource(), kunit_find_named_resource()
* and kunit_destroy_named_resource(). Resource names must be
* unique within the test instance.
*/
struct kunit_resource {
void *data;
const char *name;
kunit_resource_free_t free;
/* private: internal use only. */
struct kref refcount;
struct list_head node;
};
struct kunit;
/* Size of log associated with test. */
@ -225,6 +153,8 @@ static inline char *kunit_status_to_ok_not_ok(enum kunit_status status)
* struct kunit_suite - describes a related collection of &struct kunit_case
*
* @name: the name of the test. Purely informational.
* @suite_init: called once per test suite before the test cases.
* @suite_exit: called once per test suite after all test cases.
* @init: called before every test case.
* @exit: called after every test case.
* @test_cases: a null terminated array of test cases.
@ -239,6 +169,8 @@ static inline char *kunit_status_to_ok_not_ok(enum kunit_status status)
*/
struct kunit_suite {
const char name[256];
int (*suite_init)(struct kunit_suite *suite);
void (*suite_exit)(struct kunit_suite *suite);
int (*init)(struct kunit *test);
void (*exit)(struct kunit *test);
struct kunit_case *test_cases;
@ -247,6 +179,7 @@ struct kunit_suite {
char status_comment[KUNIT_STATUS_COMMENT_SIZE];
struct dentry *debugfs;
char *log;
int suite_init_err;
};
/**
@ -380,238 +313,39 @@ static inline int kunit_run_all_tests(void)
#define kunit_test_suite(suite) kunit_test_suites(&suite)
/**
* kunit_test_init_section_suites() - used to register one or more &struct
* kunit_suite containing init functions or
* init data.
*
* @__suites: a statically allocated list of &struct kunit_suite.
*
* This functions identically as &kunit_test_suites() except that it suppresses
* modpost warnings for referencing functions marked __init or data marked
* __initdata; this is OK because currently KUnit only runs tests upon boot
* during the init phase or upon loading a module during the init phase.
*
* NOTE TO KUNIT DEVS: If we ever allow KUnit tests to be run after boot, these
* tests must be excluded.
*
* The only thing this macro does that's different from kunit_test_suites is
* that it suffixes the array and suite declarations it makes with _probe;
* modpost suppresses warnings about referencing init data for symbols named in
* this manner.
*/
#define kunit_test_init_section_suites(__suites...) \
__kunit_test_suites(CONCATENATE(__UNIQUE_ID(array), _probe), \
CONCATENATE(__UNIQUE_ID(suites), _probe), \
##__suites)
#define kunit_test_init_section_suite(suite) \
kunit_test_init_section_suites(&suite)
#define kunit_suite_for_each_test_case(suite, test_case) \
for (test_case = suite->test_cases; test_case->run_case; test_case++)
enum kunit_status kunit_suite_has_succeeded(struct kunit_suite *suite);
/*
* Like kunit_alloc_resource() below, but returns the struct kunit_resource
* object that contains the allocation. This is mostly for testing purposes.
*/
struct kunit_resource *kunit_alloc_and_get_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
gfp_t internal_gfp,
void *context);
/**
* kunit_get_resource() - Hold resource for use. Should not need to be used
* by most users as we automatically get resources
* retrieved by kunit_find_resource*().
* @res: resource
*/
static inline void kunit_get_resource(struct kunit_resource *res)
{
kref_get(&res->refcount);
}
/*
* Called when refcount reaches zero via kunit_put_resources();
* should not be called directly.
*/
static inline void kunit_release_resource(struct kref *kref)
{
struct kunit_resource *res = container_of(kref, struct kunit_resource,
refcount);
/* If free function is defined, resource was dynamically allocated. */
if (res->free) {
res->free(res);
kfree(res);
}
}
/**
* kunit_put_resource() - When caller is done with retrieved resource,
* kunit_put_resource() should be called to drop
* reference count. The resource list maintains
* a reference count on resources, so if no users
* are utilizing a resource and it is removed from
* the resource list, it will be freed via the
* associated free function (if any). Only
* needs to be used if we alloc_and_get() or
* find() resource.
* @res: resource
*/
static inline void kunit_put_resource(struct kunit_resource *res)
{
kref_put(&res->refcount, kunit_release_resource);
}
/**
* kunit_add_resource() - Add a *test managed resource*.
* @test: The test context object.
* @init: a user-supplied function to initialize the result (if needed). If
* none is supplied, the resource data value is simply set to @data.
* If an init function is supplied, @data is passed to it instead.
* @free: a user-supplied function to free the resource (if needed).
* @res: The resource.
* @data: value to pass to init function or set in resource data field.
*/
int kunit_add_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
struct kunit_resource *res,
void *data);
/**
* kunit_add_named_resource() - Add a named *test managed resource*.
* @test: The test context object.
* @init: a user-supplied function to initialize the resource data, if needed.
* @free: a user-supplied function to free the resource data, if needed.
* @res: The resource.
* @name: name to be set for resource.
* @data: value to pass to init function or set in resource data field.
*/
int kunit_add_named_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
struct kunit_resource *res,
const char *name,
void *data);
/**
* kunit_alloc_resource() - Allocates a *test managed resource*.
* @test: The test context object.
* @init: a user supplied function to initialize the resource.
* @free: a user supplied function to free the resource.
* @internal_gfp: gfp to use for internal allocations, if unsure, use GFP_KERNEL
* @context: for the user to pass in arbitrary data to the init function.
*
* Allocates a *test managed resource*, a resource which will automatically be
* cleaned up at the end of a test case. See &struct kunit_resource for an
* example.
*
* Note: KUnit needs to allocate memory for a kunit_resource object. You must
* specify an @internal_gfp that is compatible with the use context of your
* resource.
*/
static inline void *kunit_alloc_resource(struct kunit *test,
kunit_resource_init_t init,
kunit_resource_free_t free,
gfp_t internal_gfp,
void *context)
{
struct kunit_resource *res;
res = kzalloc(sizeof(*res), internal_gfp);
if (!res)
return NULL;
if (!kunit_add_resource(test, init, free, res, context))
return res->data;
return NULL;
}
typedef bool (*kunit_resource_match_t)(struct kunit *test,
struct kunit_resource *res,
void *match_data);
/**
* kunit_resource_instance_match() - Match a resource with the same instance.
* @test: Test case to which the resource belongs.
* @res: The resource.
* @match_data: The resource pointer to match against.
*
* An instance of kunit_resource_match_t that matches a resource whose
* allocation matches @match_data.
*/
static inline bool kunit_resource_instance_match(struct kunit *test,
struct kunit_resource *res,
void *match_data)
{
return res->data == match_data;
}
/**
* kunit_resource_name_match() - Match a resource with the same name.
* @test: Test case to which the resource belongs.
* @res: The resource.
* @match_name: The name to match against.
*/
static inline bool kunit_resource_name_match(struct kunit *test,
struct kunit_resource *res,
void *match_name)
{
return res->name && strcmp(res->name, match_name) == 0;
}
/**
* kunit_find_resource() - Find a resource using match function/data.
* @test: Test case to which the resource belongs.
* @match: match function to be applied to resources/match data.
* @match_data: data to be used in matching.
*/
static inline struct kunit_resource *
kunit_find_resource(struct kunit *test,
kunit_resource_match_t match,
void *match_data)
{
struct kunit_resource *res, *found = NULL;
unsigned long flags;
spin_lock_irqsave(&test->lock, flags);
list_for_each_entry_reverse(res, &test->resources, node) {
if (match(test, res, (void *)match_data)) {
found = res;
kunit_get_resource(found);
break;
}
}
spin_unlock_irqrestore(&test->lock, flags);
return found;
}
/**
* kunit_find_named_resource() - Find a resource using match name.
* @test: Test case to which the resource belongs.
* @name: match name.
*/
static inline struct kunit_resource *
kunit_find_named_resource(struct kunit *test,
const char *name)
{
return kunit_find_resource(test, kunit_resource_name_match,
(void *)name);
}
/**
* kunit_destroy_resource() - Find a kunit_resource and destroy it.
* @test: Test case to which the resource belongs.
* @match: Match function. Returns whether a given resource matches @match_data.
* @match_data: Data passed into @match.
*
* RETURNS:
* 0 if kunit_resource is found and freed, -ENOENT if not found.
*/
int kunit_destroy_resource(struct kunit *test,
kunit_resource_match_t match,
void *match_data);
static inline int kunit_destroy_named_resource(struct kunit *test,
const char *name)
{
return kunit_destroy_resource(test, kunit_resource_name_match,
(void *)name);
}
/**
* kunit_remove_resource() - remove resource from resource list associated with
* test.
* @test: The test context object.
* @res: The resource to be removed.
*
* Note that the resource will not be immediately freed since it is likely
* the caller has a reference to it via alloc_and_get() or find();
* in this case a final call to kunit_put_resource() is required.
*/
void kunit_remove_resource(struct kunit *test, struct kunit_resource *res);
/**
* kunit_kmalloc_array() - Like kmalloc_array() except the allocation is *test managed*.
* @test: The test context object.
@ -774,7 +508,7 @@ void __printf(2, 3) kunit_log_append(char *log, const char *fmt, ...);
void kunit_do_failed_assertion(struct kunit *test,
const struct kunit_loc *loc,
enum kunit_assert_type type,
struct kunit_assert *assert,
const struct kunit_assert *assert,
const char *fmt, ...);
#define KUNIT_ASSERTION(test, assert_type, pass, assert_class, INITIALIZER, fmt, ...) do { \
@ -1218,6 +952,48 @@ do { \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_EXPECT_NULL() - Expects that @ptr is null.
* @test: The test context object.
* @ptr: an arbitrary pointer.
*
* Sets an expectation that the value that @ptr evaluates to is null. This is
* semantically equivalent to KUNIT_EXPECT_PTR_EQ(@test, ptr, NULL).
* See KUNIT_EXPECT_TRUE() for more information.
*/
#define KUNIT_EXPECT_NULL(test, ptr) \
KUNIT_EXPECT_NULL_MSG(test, \
ptr, \
NULL)
#define KUNIT_EXPECT_NULL_MSG(test, ptr, fmt, ...) \
KUNIT_BINARY_PTR_ASSERTION(test, \
KUNIT_EXPECTATION, \
ptr, ==, NULL, \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_EXPECT_NOT_NULL() - Expects that @ptr is not null.
* @test: The test context object.
* @ptr: an arbitrary pointer.
*
* Sets an expectation that the value that @ptr evaluates to is not null. This
* is semantically equivalent to KUNIT_EXPECT_PTR_NE(@test, ptr, NULL).
* See KUNIT_EXPECT_TRUE() for more information.
*/
#define KUNIT_EXPECT_NOT_NULL(test, ptr) \
KUNIT_EXPECT_NOT_NULL_MSG(test, \
ptr, \
NULL)
#define KUNIT_EXPECT_NOT_NULL_MSG(test, ptr, fmt, ...) \
KUNIT_BINARY_PTR_ASSERTION(test, \
KUNIT_EXPECTATION, \
ptr, !=, NULL, \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_EXPECT_NOT_ERR_OR_NULL() - Expects that @ptr is not null and not err.
* @test: The test context object.
@ -1485,6 +1261,48 @@ do { \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_ASSERT_NULL() - Asserts that pointers @ptr is null.
* @test: The test context object.
* @ptr: an arbitrary pointer.
*
* Sets an assertion that the values that @ptr evaluates to is null. This is
* the same as KUNIT_EXPECT_NULL(), except it causes an assertion
* failure (see KUNIT_ASSERT_TRUE()) when the assertion is not met.
*/
#define KUNIT_ASSERT_NULL(test, ptr) \
KUNIT_ASSERT_NULL_MSG(test, \
ptr, \
NULL)
#define KUNIT_ASSERT_NULL_MSG(test, ptr, fmt, ...) \
KUNIT_BINARY_PTR_ASSERTION(test, \
KUNIT_ASSERTION, \
ptr, ==, NULL, \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_ASSERT_NOT_NULL() - Asserts that pointers @ptr is not null.
* @test: The test context object.
* @ptr: an arbitrary pointer.
*
* Sets an assertion that the values that @ptr evaluates to is not null. This
* is the same as KUNIT_EXPECT_NOT_NULL(), except it causes an assertion
* failure (see KUNIT_ASSERT_TRUE()) when the assertion is not met.
*/
#define KUNIT_ASSERT_NOT_NULL(test, ptr) \
KUNIT_ASSERT_NOT_NULL_MSG(test, \
ptr, \
NULL)
#define KUNIT_ASSERT_NOT_NULL_MSG(test, ptr, fmt, ...) \
KUNIT_BINARY_PTR_ASSERTION(test, \
KUNIT_ASSERTION, \
ptr, !=, NULL, \
fmt, \
##__VA_ARGS__)
/**
* KUNIT_ASSERT_NOT_ERR_OR_NULL() - Assertion that @ptr is not null and not err.
* @test: The test context object.
@ -1526,4 +1344,8 @@ do { \
return NULL; \
}
// TODO(dlatypov@google.com): consider eventually migrating users to explicitly
// include resource.h themselves if they need it.
#include <kunit/resource.h>
#endif /* _KUNIT_TEST_H */

2
include/kvm/arm_arch_timer.h
View file

@ -76,8 +76,6 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
bool kvm_timer_is_pending(struct kvm_vcpu *vcpu);
u64 kvm_phys_timer_read(void);
void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu);

8
include/kvm/arm_hypercalls.h
View file

@ -40,4 +40,12 @@ static inline void smccc_set_retval(struct kvm_vcpu *vcpu,
vcpu_set_reg(vcpu, 3, a3);
}
struct kvm_one_reg;
void kvm_arm_init_hypercalls(struct kvm *kvm);
int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu);
int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
#endif

34
include/kvm/arm_pmu.h
View file

@ -20,13 +20,19 @@ struct kvm_pmc {
struct perf_event *perf_event;
};
struct kvm_pmu_events {
u32 events_host;
u32 events_guest;
};
struct kvm_pmu {
int irq_num;
struct irq_work overflow_work;
struct kvm_pmu_events events;
struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
int irq_num;
bool created;
bool irq_level;
struct irq_work overflow_work;
};
struct arm_pmu_entry {
@ -66,6 +72,25 @@ int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
struct kvm_pmu_events *kvm_get_pmu_events(void);
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
#define kvm_vcpu_has_pmu(vcpu) \
(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
/*
* Updates the vcpu's view of the pmu events for this cpu.
* Must be called before every vcpu run after disabling interrupts, to ensure
* that an interrupt cannot fire and update the structure.
*/
#define kvm_pmu_update_vcpu_events(vcpu) \
do { \
if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \
vcpu->arch.pmu.events = *kvm_get_pmu_events(); \
} while (0)
#else
struct kvm_pmu {
};
@ -127,6 +152,11 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
return 0;
}
#define kvm_vcpu_has_pmu(vcpu) ({ false; })
static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
#endif
#endif

7
include/kvm/arm_psci.h
View file

@ -39,11 +39,4 @@ static inline int kvm_psci_version(struct kvm_vcpu *vcpu)
int kvm_psci_call(struct kvm_vcpu *vcpu);
struct kvm_one_reg;
int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu);
int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
#endif /* __KVM_ARM_PSCI_H__ */

8
include/kvm/arm_vgic.h
View file

@ -231,6 +231,9 @@ struct vgic_dist {
/* Implementation revision as reported in the GICD_IIDR */
u32 implementation_rev;
#define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */
#define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */
#define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3
/* Userspace can write to GICv2 IGROUPR */
bool v2_groups_user_writable;
@ -344,11 +347,12 @@ struct vgic_cpu {
struct vgic_io_device rd_iodev;
struct vgic_redist_region *rdreg;
u32 rdreg_index;
atomic_t syncr_busy;
/* Contains the attributes and gpa of the LPI pending tables. */
u64 pendbaser;
bool lpis_enabled;
/* GICR_CTLR.{ENABLE_LPIS,RWP} */
atomic_t ctlr;
/* Cache guest priority bits */
u32 num_pri_bits;

1
include/linux/acct.h
View file

@ -21,7 +21,6 @@
#ifdef CONFIG_BSD_PROCESS_ACCT
struct pid_namespace;
extern int acct_parm[]; /* for sysctl */
extern void acct_collect(long exitcode, int group_dead);
extern void acct_process(void);
extern void acct_exit_ns(struct pid_namespace *);

47
include/linux/acpi.h
View file

@ -520,9 +520,6 @@ int acpi_check_resource_conflict(const struct resource *res);
int acpi_check_region(resource_size_t start, resource_size_t n,
const char *name);
acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,
u32 level);
int acpi_resources_are_enforced(void);
#ifdef CONFIG_HIBERNATION
@ -550,10 +547,16 @@ struct acpi_osc_context {
acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
/* Indexes into _OSC Capabilities Buffer (DWORDs 2 & 3 are device-specific) */
/* Number of _OSC capability DWORDS depends on bridge type */
#define OSC_PCI_CAPABILITY_DWORDS 3
#define OSC_CXL_CAPABILITY_DWORDS 5
/* Indexes into _OSC Capabilities Buffer (DWORDs 2 to 5 are device-specific) */
#define OSC_QUERY_DWORD 0 /* DWORD 1 */
#define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
#define OSC_CONTROL_DWORD 2 /* DWORD 3 */
#define OSC_EXT_SUPPORT_DWORD 3 /* DWORD 4 */
#define OSC_EXT_CONTROL_DWORD 4 /* DWORD 5 */
/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
#define OSC_QUERY_ENABLE 0x00000001 /* input */
@ -574,6 +577,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
#define OSC_SB_OSLPI_SUPPORT 0x00000100
#define OSC_SB_CPC_DIVERSE_HIGH_SUPPORT 0x00001000
#define OSC_SB_GENERIC_INITIATOR_SUPPORT 0x00002000
#define OSC_SB_CPC_FLEXIBLE_ADR_SPACE 0x00004000
#define OSC_SB_NATIVE_USB4_SUPPORT 0x00040000
#define OSC_SB_PRM_SUPPORT 0x00200000
@ -581,6 +585,7 @@ extern bool osc_sb_apei_support_acked;
extern bool osc_pc_lpi_support_confirmed;
extern bool osc_sb_native_usb4_support_confirmed;
extern bool osc_sb_cppc_not_supported;
extern bool osc_cpc_flexible_adr_space_confirmed;
/* USB4 Capabilities */
#define OSC_USB_USB3_TUNNELING 0x00000001
@ -608,6 +613,29 @@ extern u32 osc_sb_native_usb4_control;
#define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020
#define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080
/* CXL _OSC: Capabilities DWORD 4: Support Field */
#define OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT 0x00000001
#define OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT 0x00000002
#define OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT 0x00000004
#define OSC_CXL_NATIVE_HP_SUPPORT 0x00000008
/* CXL _OSC: Capabilities DWORD 5: Control Field */
#define OSC_CXL_ERROR_REPORTING_CONTROL 0x00000001
static inline u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
{
u32 *ret = context->ret.pointer;
return ret[OSC_CONTROL_DWORD];
}
static inline u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
{
u32 *ret = context->ret.pointer;
return ret[OSC_EXT_CONTROL_DWORD];
}
#define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
#define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
@ -1004,6 +1032,17 @@ static inline int acpi_register_wakeup_handler(int wake_irq,
static inline void acpi_unregister_wakeup_handler(
bool (*wakeup)(void *context), void *context) { }
struct acpi_osc_context;
static inline u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
{
return 0;
}
static inline u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
{
return 0;
}
#endif /* !CONFIG_ACPI */
#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC

14
include/linux/amba/bus.h
View file

@ -70,7 +70,11 @@ struct amba_device {
unsigned int cid;
struct amba_cs_uci_id uci;
unsigned int irq[AMBA_NR_IRQS];
char *driver_override;
/*
* Driver name to force a match. Do not set directly, because core
* frees it. Use driver_set_override() to set or clear it.
*/
const char *driver_override;
};
struct amba_driver {
@ -79,6 +83,14 @@ struct amba_driver {
void (*remove)(struct amba_device *);
void (*shutdown)(struct amba_device *);
const struct amba_id *id_table;
/*
* For most device drivers, no need to care about this flag as long as
* all DMAs are handled through the kernel DMA API. For some special
* ones, for example VFIO drivers, they know how to manage the DMA
* themselves and set this flag so that the IOMMU layer will allow them
* to setup and manage their own I/O address space.
*/
bool driver_managed_dma;
};
/*

6
include/linux/amba/mmci.h
View file

@ -13,17 +13,11 @@
* @ocr_mask: available voltages on the 4 pins from the block, this
* is ignored if a regulator is used, see the MMC_VDD_* masks in
* mmc/host.h
* @ios_handler: a callback function to act on specfic ios changes,
* used for example to control a levelshifter
* mask into a value to be binary (or set some other custom bits
* in MMCIPWR) or:ed and written into the MMCIPWR register of the
* block. May also control external power based on the power_mode.
* @status: if no GPIO line was given to the block in this function will
* be called to determine whether a card is present in the MMC slot or not
*/
struct mmci_platform_data {
unsigned int ocr_mask;
int (*ios_handler)(struct device *, struct mmc_ios *);
unsigned int (*status)(struct device *);
};

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