ARM: pxa: move platform_data definitions

Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.

This moves such data out of the pxa include directories

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Paul Parsons <lost.distance@yahoo.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Acked-By: Stefan Schmidt <stefan@openezx.org>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Ribeiro <drwyrm@gmail.com>
Cc: Harald Welte <laforge@openezx.org>
Cc: Philipp Zabel <philipp.zabel@gmail.com>
Cc: Tomas Cech <sleep_walker@suse.cz>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Jonathan Cameron <jic23@cam.ac.uk>
Cc: Dan Williams <djbw@fb.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Samuel Ortiz <samuel@sortiz.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: openezx-devel@lists.openezx.org
This commit is contained in:
Arnd Bergmann 2012-08-24 15:16:48 +02:00
parent 2960ed3468
commit 293b2da1b6
86 changed files with 188 additions and 188 deletions

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#ifndef _INCLUDE_PALMASOC_H_
#define _INCLUDE_PALMASOC_H_
struct palm27x_asoc_info {
int jack_gpio;
};
#endif

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/*
* Generic PXA PATA driver
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_PATA_PXA_H__
#define __MACH_PATA_PXA_H__
struct pata_pxa_pdata {
/* PXA DMA DREQ<0:2> pin */
uint32_t dma_dreq;
/* Register shift */
uint32_t reg_shift;
/* IRQ flags */
uint32_t irq_flags;
};
#endif /* __MACH_PATA_PXA_H__ */

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/*
camera.h - PXA camera driver header file
Copyright (C) 2003, Intel Corporation
Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#define PXA_CAMERA_MASTER 1
#define PXA_CAMERA_DATAWIDTH_4 2
#define PXA_CAMERA_DATAWIDTH_5 4
#define PXA_CAMERA_DATAWIDTH_8 8
#define PXA_CAMERA_DATAWIDTH_9 0x10
#define PXA_CAMERA_DATAWIDTH_10 0x20
#define PXA_CAMERA_PCLK_EN 0x40
#define PXA_CAMERA_MCLK_EN 0x80
#define PXA_CAMERA_PCP 0x100
#define PXA_CAMERA_HSP 0x200
#define PXA_CAMERA_VSP 0x400
struct pxacamera_platform_data {
unsigned long flags;
unsigned long mclk_10khz;
};
extern void pxa_set_camera_info(struct pxacamera_platform_data *);
#endif /* __ASM_ARCH_CAMERA_H_ */

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/*
* linux/arch/arm/mach-mmp/include/mach/sram.h
*
* SRAM Memory Management
*
* Copyright (c) 2011 Marvell Semiconductors Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_SRAM_H
#define __ASM_ARCH_SRAM_H
#include <linux/genalloc.h>
/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
#define SRAM_GRANULARITY 512
enum sram_type {
MMP_SRAM_UNDEFINED = 0,
MMP_ASRAM,
MMP_ISRAM,
};
struct sram_platdata {
char *pool_name;
int granularity;
};
extern struct gen_pool *sram_get_gpool(char *pool_name);
#endif /* __ASM_ARCH_SRAM_H */

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#ifndef ASMARM_ARCH_IRDA_H
#define ASMARM_ARCH_IRDA_H
/* board specific transceiver capabilities */
#define IR_OFF 1
#define IR_SIRMODE 2
#define IR_FIRMODE 4
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
int (*startup)(struct device *dev);
void (*shutdown)(struct device *dev);
int gpio_pwdown; /* powerdown GPIO for the IrDA chip */
bool gpio_pwdown_inverted; /* gpio_pwdown is inverted */
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
void pxa2xx_transceiver_mode(struct device *dev, int mode);
#endif
#endif

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#ifndef __ASM_ARCH_PXA930_ROTARY_H
#define __ASM_ARCH_PXA930_ROTARY_H
/* NOTE:
*
* rotary can be either interpreted as a ralative input event (e.g.
* REL_WHEEL or REL_HWHEEL) or a specific key event (e.g. UP/DOWN
* or LEFT/RIGHT), depending on if up_key & down_key are assigned
* or rel_code is assigned a non-zero value. When all are non-zero,
* up_key and down_key will be preferred.
*/
struct pxa930_rotary_platform_data {
int up_key;
int down_key;
int rel_code;
};
void __init pxa930_set_rotarykey_info(struct pxa930_rotary_platform_data *info);
#endif /* __ASM_ARCH_PXA930_ROTARY_H */

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#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
#define __ASM_ARCH_PXA27x_KEYPAD_H
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#define MAX_MATRIX_KEY_ROWS (8)
#define MAX_MATRIX_KEY_COLS (8)
#define MATRIX_ROW_SHIFT (3)
#define MAX_DIRECT_KEY_NUM (8)
/* pxa3xx keypad platform specific parameters
*
* NOTE:
* 1. direct_key_num indicates the number of keys in the direct keypad
* _plus_ the number of rotary-encoder sensor inputs, this can be
* left as 0 if only rotary encoders are enabled, the driver will
* automatically calculate this
*
* 2. direct_key_map is the key code map for the direct keys, if rotary
* encoder(s) are enabled, direct key 0/1(2/3) will be ignored
*
* 3. rotary can be either interpreted as a relative input event (e.g.
* REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
*
* 4. matrix key and direct key will use the same debounce_interval by
* default, which should be sufficient in most cases
*
* pxa168 keypad platform specific parameter
*
* NOTE:
* clear_wakeup_event callback is a workaround required to clear the
* keypad interrupt. The keypad wake must be cleared in addition to
* reading the MI/DI bits in the KPC register.
*/
struct pxa27x_keypad_platform_data {
/* code map for the matrix keys */
unsigned int matrix_key_rows;
unsigned int matrix_key_cols;
unsigned int *matrix_key_map;
int matrix_key_map_size;
/* direct keys */
int direct_key_num;
unsigned int direct_key_map[MAX_DIRECT_KEY_NUM];
/* the key output may be low active */
int direct_key_low_active;
/* give board a chance to choose the start direct key */
unsigned int direct_key_mask;
/* rotary encoders 0 */
int enable_rotary0;
int rotary0_rel_code;
int rotary0_up_key;
int rotary0_down_key;
/* rotary encoders 1 */
int enable_rotary1;
int rotary1_rel_code;
int rotary1_up_key;
int rotary1_down_key;
/* key debounce interval */
unsigned int debounce_interval;
/* clear wakeup event requirement for pxa168 */
void (*clear_wakeup_event)(void);
};
extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */

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#ifndef ASMARM_ARCH_MMC_H
#define ASMARM_ARCH_MMC_H
#include <linux/mmc/host.h>
#include <linux/interrupt.h>
struct device;
struct mmc_host;
struct pxamci_platform_data {
unsigned int ocr_mask; /* available voltages */
unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
int (*init)(struct device *, irq_handler_t , void *);
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
void (*exit)(struct device *, void *);
int gpio_card_detect; /* gpio detecting card insertion */
int gpio_card_ro; /* gpio detecting read only toggle */
bool gpio_card_ro_invert; /* gpio ro is inverted */
int gpio_power; /* gpio powering up MMC bus */
bool gpio_power_invert; /* gpio power is inverted */
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
#endif

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#ifndef __ASM_ARCH_PXA930_TRKBALL_H
#define __ASM_ARCH_PXA930_TRKBALL_H
struct pxa930_trkball_platform_data {
int x_filter;
int y_filter;
};
#endif /* __ASM_ARCH_PXA930_TRKBALL_H */

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#ifndef __ASM_ARCH_PXA3XX_NAND_H
#define __ASM_ARCH_PXA3XX_NAND_H
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
struct pxa3xx_nand_timing {
unsigned int tCH; /* Enable signal hold time */
unsigned int tCS; /* Enable signal setup time */
unsigned int tWH; /* ND_nWE high duration */
unsigned int tWP; /* ND_nWE pulse time */
unsigned int tRH; /* ND_nRE high duration */
unsigned int tRP; /* ND_nRE pulse width */
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
};
struct pxa3xx_nand_cmdset {
uint16_t read1;
uint16_t read2;
uint16_t program;
uint16_t read_status;
uint16_t read_id;
uint16_t erase;
uint16_t reset;
uint16_t lock;
uint16_t unlock;
uint16_t lock_status;
};
struct pxa3xx_nand_flash {
char *name;
uint32_t chip_id;
unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
unsigned int num_blocks; /* Number of physical blocks in Flash */
struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
};
/*
* Current pxa3xx_nand controller has two chip select which
* both be workable.
*
* Notice should be taken that:
* When you want to use this feature, you should not enable the
* keep configuration feature, for two chip select could be
* attached with different nand chip. The different page size
* and timing requirement make the keep configuration impossible.
*/
/* The max num of chip select current support */
#define NUM_CHIP_SELECT (2)
struct pxa3xx_nand_platform_data {
/* the data flash bus is shared between the Static Memory
* Controller and the Data Flash Controller, the arbiter
* controls the ownership of the bus
*/
int enable_arbiter;
/* allow platform code to keep OBM/bootloader defined NFC config */
int keep_config;
/* indicate how many chip selects will be used */
int num_cs;
const struct mtd_partition *parts[NUM_CHIP_SELECT];
unsigned int nr_parts[NUM_CHIP_SELECT];
const struct pxa3xx_nand_flash * flash;
size_t num_flash;
};
extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
#endif /* __ASM_ARCH_PXA3XX_NAND_H */

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#ifndef __ARCOM_PCMCIA_H
#define __ARCOM_PCMCIA_H
struct arcom_pcmcia_pdata {
int cd_gpio;
int rdy_gpio;
int pwr_gpio;
void (*reset)(int state);
};
#endif

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#ifndef ASMARM_ARCH_OHCI_H
#define ASMARM_ARCH_OHCI_H
struct device;
struct pxaohci_platform_data {
int (*init)(struct device *);
void (*exit)(struct device *);
unsigned long flags;
#define ENABLE_PORT1 (1 << 0)
#define ENABLE_PORT2 (1 << 1)
#define ENABLE_PORT3 (1 << 2)
#define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
#define POWER_SENSE_LOW (1 << 3)
#define POWER_CONTROL_LOW (1 << 4)
#define NO_OC_PROTECTION (1 << 5)
#define OC_MODE_GLOBAL (0 << 6)
#define OC_MODE_PERPORT (1 << 6)
int power_on_delay; /* Power On to Power Good time - in ms
* HCD must wait for this duration before
* accessing a powered on port
*/
int port_mode;
#define PMM_NPS_MODE 1
#define PMM_GLOBAL_MODE 2
#define PMM_PERPORT_MODE 3
int power_budget;
};
extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
#endif

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/*
* PXA3xx U2D header
*
* Copyright (C) 2010 CompuLab Ltd.
*
* Igor Grinberg <grinberg@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PXA310_U2D__
#define __PXA310_U2D__
#include <linux/usb/ulpi.h>
struct pxa3xx_u2d_platform_data {
#define ULPI_SER_6PIN (1 << 0)
#define ULPI_SER_3PIN (1 << 1)
unsigned int ulpi_mode;
int (*init)(struct device *);
void (*exit)(struct device *);
};
/* Start PXA3xx U2D host */
int pxa3xx_u2d_start_hc(struct usb_bus *host);
/* Stop PXA3xx U2D host */
void pxa3xx_u2d_stop_hc(struct usb_bus *host);
extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
#endif /* __PXA310_U2D__ */

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/*
* arch/arm/mach-pxa/include/mach/pxafb.h
*
* Support for the xscale frame buffer.
*
* Author: Jean-Frederic Clere
* Created: Sep 22, 2003
* Copyright: jfclere@sinix.net
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <mach/regs-lcd.h>
/*
* Supported LCD connections
*
* bits 0 - 3: for LCD panel type:
*
* STN - for passive matrix
* DSTN - for dual scan passive matrix
* TFT - for active matrix
*
* bits 4 - 9 : for bus width
* bits 10-17 : for AC Bias Pin Frequency
* bit 18 : for output enable polarity
* bit 19 : for pixel clock edge
* bit 20 : for output pixel format when base is RGBT16
*/
#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
#define LCD_TYPE_MASK 0xf
#define LCD_TYPE_UNKNOWN 0
#define LCD_TYPE_MONO_STN 1
#define LCD_TYPE_MONO_DSTN 2
#define LCD_TYPE_COLOR_STN 3
#define LCD_TYPE_COLOR_DSTN 4
#define LCD_TYPE_COLOR_TFT 5
#define LCD_TYPE_SMART_PANEL 6
#define LCD_TYPE_MAX 7
#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
#define LCD_BIAS_ACTIVE_HIGH (0 << 18)
#define LCD_BIAS_ACTIVE_LOW (1 << 18)
#define LCD_PCLK_EDGE_RISE (0 << 19)
#define LCD_PCLK_EDGE_FALL (1 << 19)
#define LCD_ALTERNATE_MAPPING (1 << 20)
/*
* This structure describes the machine which we are running on.
* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
* of linux/drivers/video/pxafb.c
*/
struct pxafb_mode_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_int cmap_greyscale:1,
depth:8,
transparency:1,
unused:22;
/* Parallel Mode Timing */
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
* Note:
* 1. all parameters in nanosecond (ns)
* 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
* in pxa27x and pxa3xx, initialize them to the same value or
* the larger one will be used
* 3. same to {rd,wr}_pulse_width
*
* 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
* 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
* 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
*/
unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
unsigned cmd_inh_time; /* Command Inhibit time between two writes */
unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
};
struct pxafb_mach_info {
struct pxafb_mode_info *modes;
unsigned int num_modes;
unsigned int lcd_conn;
unsigned long video_mem_size;
u_int fixed_modes:1,
cmap_inverse:1,
cmap_static:1,
acceleration_enabled:1,
unused:28;
/* The following should be defined in LCCR0
* LCCR0_Act or LCCR0_Pas Active or Passive
* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
* LCCR0_Mono or LCCR0_Color Mono/Color
* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
* LCCR0_DMADel(Tcpu) (optional) DMA request delay
*
* The following should not be defined in LCCR0:
* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
*/
u_int lccr0;
/* The following should be defined in LCCR3
* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
* LCCR3_Acb(X) AB Bias pin frequency
* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
*
* The following should not be defined in LCCR3
* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
*/
u_int lccr3;
/* The following should be defined in LCCR4
* LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
*
* All other bits in LCCR4 should be left alone.
*/
u_int lccr4;
void (*pxafb_backlight_power)(int);
void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
void (*smart_update)(struct fb_info *);
};
void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
unsigned long pxafb_get_hsync_time(struct device *dev);
#ifdef CONFIG_FB_PXA_SMARTPANEL
extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
extern int pxafb_smart_flush(struct fb_info *info);
#else
static inline int pxafb_smart_queue(struct fb_info *info,
uint16_t *cmds, int n)
{
return 0;
}
static inline int pxafb_smart_flush(struct fb_info *info)
{
return 0;
}
#endif