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iio: adc: ti-adc0832: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: efc945fb72 ("iio: adc: add support for ADC0831/ADC0832/ADC0834/ADC0838 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-29-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:08 +01:00
parent e770f78036
commit 1e6bb81c23
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/adc/ti-adc0832.c
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@ -36,7 +36,7 @@ struct adc0832 {
*/
u8 data[24] __aligned(8);
u8 tx_buf[2] ____cacheline_aligned;
u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
u8 rx_buf[2];
};