Merge remote-tracking branch 'spi/for-5.14' into spi-next
This commit is contained in:
Mark Brown
commit
1bee1ecf23
57 changed files with 1249 additions and 862 deletions
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@ -170,6 +170,28 @@ struct spinand_op;
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struct spinand_device;
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#define SPINAND_MAX_ID_LEN 4
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/*
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* For erase, write and read operation, we got the following timings :
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* tBERS (erase) 1ms to 4ms
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* tPROG 300us to 400us
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* tREAD 25us to 100us
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* In order to minimize latency, the min value is divided by 4 for the
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* initial delay, and dividing by 20 for the poll delay.
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* For reset, 5us/10us/500us if the device is respectively
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* reading/programming/erasing when the RESET occurs. Since we always
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* issue a RESET when the device is IDLE, 5us is selected for both initial
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* and poll delay.
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*/
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#define SPINAND_READ_INITIAL_DELAY_US 6
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#define SPINAND_READ_POLL_DELAY_US 5
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#define SPINAND_RESET_INITIAL_DELAY_US 5
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#define SPINAND_RESET_POLL_DELAY_US 5
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#define SPINAND_WRITE_INITIAL_DELAY_US 75
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#define SPINAND_WRITE_POLL_DELAY_US 15
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#define SPINAND_ERASE_INITIAL_DELAY_US 250
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#define SPINAND_ERASE_POLL_DELAY_US 50
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#define SPINAND_WAITRDY_TIMEOUT_MS 400
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/**
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* struct spinand_id - SPI NAND id structure
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@ -1,16 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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*/
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#ifndef _ATH79_SPI_PLATFORM_H
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#define _ATH79_SPI_PLATFORM_H
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struct ath79_spi_platform_data {
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unsigned bus_num;
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unsigned num_chipselect;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This driver supports the following PXA CPU/SSP ports:-
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*
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@ -11,8 +11,8 @@
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* PXA3xx SSP1, SSP2, SSP3, SSP4
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*/
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#ifndef __LINUX_SSP_H
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#define __LINUX_SSP_H
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#ifndef __LINUX_PXA2XX_SSP_H
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#define __LINUX_PXA2XX_SSP_H
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#include <linux/bits.h>
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#include <linux/compiler_types.h>
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@ -38,7 +38,6 @@ struct device_node;
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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@ -60,7 +59,7 @@ struct device_node;
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/* PXA27x, PXA3xx */
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#define SSCR0_EDSS BIT(20) /* Extended data size select */
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#define SSCR0_NCS BIT(21) /* Network clock select */
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#define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */
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#define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
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#define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
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#define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
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#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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@ -105,6 +104,9 @@ struct device_node;
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#define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */
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#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
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/* Intel Quark X1000 */
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#define DDS_RATE 0x28 /* SSP DDS Clock Rate Register */
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/* QUARK_X1000 SSCR0 bit definition */
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#define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */
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#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
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@ -124,7 +126,7 @@ struct device_node;
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#define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
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#define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */
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/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
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/* Extra bits in PXA255, PXA26x and PXA27x SSP ports */
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#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
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#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
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@ -181,6 +183,21 @@ struct device_node;
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#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
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#define SSACD_SCDX8 BIT(7) /* SYSCLK division ratio select */
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/* Intel Merrifield SSP */
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#define SFIFOL 0x68 /* FIFO level */
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#define SFIFOTT 0x6c /* FIFO trigger threshold */
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#define RX_THRESH_MRFLD_DFLT 16
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#define TX_THRESH_MRFLD_DFLT 16
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#define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */
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#define SFIFOL_RFL_MASK GENMASK(31, 16) /* Receive FIFO Level mask */
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#define SFIFOTT_TFT GENMASK(15, 0) /* Transmit FIFO Threshold (mask) */
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#define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */
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#define SFIFOTT_RFT GENMASK(31, 16) /* Receive FIFO Threshold (mask) */
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#define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */
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/* LPSS SSP */
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#define SSITF 0x44 /* TX FIFO trigger level */
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#define SSITF_TxHiThresh(x) (((x) - 1) << 0)
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@ -203,8 +220,10 @@ enum pxa_ssp_type {
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MMP2_SSP,
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PXA910_SSP,
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CE4100_SSP,
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MRFLD_SSP,
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QUARK_X1000_SSP,
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LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
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/* Keep LPSS types sorted with lpss_platforms[] */
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LPSS_LPT_SSP,
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LPSS_BYT_SSP,
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LPSS_BSW_SSP,
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LPSS_SPT_SSP,
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@ -252,6 +271,22 @@ static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
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return __raw_readl(dev->mmio_base + reg);
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}
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static inline void pxa_ssp_enable(struct ssp_device *ssp)
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{
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u32 sscr0;
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sscr0 = pxa_ssp_read_reg(ssp, SSCR0) | SSCR0_SSE;
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pxa_ssp_write_reg(ssp, SSCR0, sscr0);
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}
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static inline void pxa_ssp_disable(struct ssp_device *ssp)
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{
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u32 sscr0;
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sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~SSCR0_SSE;
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pxa_ssp_write_reg(ssp, SSCR0, sscr0);
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}
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#if IS_ENABLED(CONFIG_PXA_SSP)
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struct ssp_device *pxa_ssp_request(int port, const char *label);
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void pxa_ssp_free(struct ssp_device *);
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@ -270,4 +305,4 @@ static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
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static inline void pxa_ssp_free(struct ssp_device *ssp) {}
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#endif
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#endif
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#endif /* __LINUX_PXA2XX_SSP_H */
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@ -2,8 +2,10 @@
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/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*/
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#ifndef __linux_pxa2xx_spi_h
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#define __linux_pxa2xx_spi_h
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#ifndef __LINUX_SPI_PXA2XX_SPI_H
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#define __LINUX_SPI_PXA2XX_SPI_H
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#include <linux/types.h>
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#include <linux/pxa2xx_ssp.h>
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@ -12,7 +14,10 @@
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struct dma_chan;
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/* device.platform_data for SSP controller devices */
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/*
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* The platform data for SSP controller devices
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* (resides in device.platform_data).
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*/
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struct pxa2xx_spi_controller {
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u16 num_chipselect;
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u8 enable_dma;
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@ -28,8 +33,11 @@ struct pxa2xx_spi_controller {
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struct ssp_device ssp;
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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/*
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* The controller specific data for SPI slave devices
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* (resides in spi_board_info.controller_data),
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* copied to spi_device.platform_data ... mostly for
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* DMA tuning.
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*/
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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@ -49,4 +57,5 @@ struct pxa2xx_spi_chip {
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extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_controller *info);
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#endif
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#endif
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#endif /* __LINUX_SPI_PXA2XX_SPI_H */
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@ -250,6 +250,9 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
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* the currently mapped area), and the caller of
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* spi_mem_dirmap_write() is responsible for calling it again in
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* this case.
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* @poll_status: poll memory device status until (status & mask) == match or
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* when the timeout has expired. It fills the data buffer with
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* the last status value.
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*
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* This interface should be implemented by SPI controllers providing an
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* high-level interface to execute SPI memory operation, which is usually the
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@ -274,6 +277,12 @@ struct spi_controller_mem_ops {
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u64 offs, size_t len, void *buf);
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ssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, const void *buf);
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int (*poll_status)(struct spi_mem *mem,
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const struct spi_mem_op *op,
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u16 mask, u16 match,
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unsigned long initial_delay_us,
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unsigned long polling_rate_us,
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unsigned long timeout_ms);
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};
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/**
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@ -369,6 +378,13 @@ devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem,
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void devm_spi_mem_dirmap_destroy(struct device *dev,
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struct spi_mem_dirmap_desc *desc);
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int spi_mem_poll_status(struct spi_mem *mem,
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const struct spi_mem_op *op,
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u16 mask, u16 match,
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unsigned long initial_delay_us,
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unsigned long polling_delay_us,
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u16 timeout_ms);
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int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
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struct module *owner);
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@ -299,6 +299,8 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
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driver_unregister(&sdrv->driver);
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}
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extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select);
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/* use a define to avoid include chaining to get THIS_MODULE */
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#define spi_register_driver(driver) \
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__spi_register_driver(THIS_MODULE, driver)
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@ -586,6 +588,7 @@ struct spi_controller {
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bool (*can_dma)(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer);
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struct device *dma_map_dev;
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/*
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* These hooks are for drivers that want to use the generic
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@ -1108,11 +1111,6 @@ static inline void spi_message_free(struct spi_message *m)
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kfree(m);
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}
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extern int spi_set_cs_timing(struct spi_device *spi,
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struct spi_delay *setup,
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struct spi_delay *hold,
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struct spi_delay *inactive);
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extern int spi_setup(struct spi_device *spi);
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extern int spi_async(struct spi_device *spi, struct spi_message *message);
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extern int spi_async_locked(struct spi_device *spi,
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