Arm SMMU updates for 5.10
- Continued SVM enablement, where page-table is shared with CPU - Groundwork to support integrated SMMU with Adreno GPU - Allow disabling of MSI-based polling on the kernel command-line - Minor driver fixes and cleanups (octal permissions, error messages, ...) -----BEGIN PGP SIGNATURE----- iQFEBAABCgAuFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAl9zsywQHHdpbGxAa2Vy bmVsLm9yZwAKCRC3rHDchMFjNKQfCAC8I2qShq+uMC6YnNeVBPhNRQzI+BsCpqqv 8odxxE7v+eIJs6nUtaV50MMfXeZn2oZcU7RPVHFJ6bd9p77aTTD17BRMLV/L+/aO JrE/oS+KLf9FyPMlYd/GTJvznIEyYaTvhB8HHzfUUwMdw3t/Wa/vbefNqv1CcD1t r4qwpc/yj6fdjaVEcatAr8H0Df4pWEArmmyW8VerGpQ5TFxoW7vHTaiHLflOAf69 nZfUAQpVC/45pjbXQct6FBp72UboMwDZnsQBjr+on9eXUP9nZ6Jz+3cXwRILO6jm 7urbeHaer8dp+whJexfR6GdBvShcJ6fWSYtBZCERu6pbUTIrD+LE =jYVP -----END PGP SIGNATURE----- Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu Arm SMMU updates for 5.10 - Continued SVM enablement, where page-table is shared with CPU - Groundwork to support integrated SMMU with Adreno GPU - Allow disabling of MSI-based polling on the kernel command-line - Minor driver fixes and cleanups (octal permissions, error messages, ...)
This commit is contained in:
Joerg Roedel
commit
0dd4ce65aa
18 changed files with 1411 additions and 799 deletions
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@ -1506,8 +1506,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/iommu/arm,smmu*
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F: drivers/iommu/arm/
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F: drivers/iommu/io-pgtable-arm-v7s.c
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F: drivers/iommu/io-pgtable-arm.c
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F: drivers/iommu/io-pgtable-arm*
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ARM SUB-ARCHITECTURES
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -45,6 +45,7 @@
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#define rmb() dsb(ld)
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#define wmb() dsb(st)
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#define dma_mb() dmb(osh)
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#define dma_rmb() dmb(oshld)
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#define dma_wmb() dmb(oshst)
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@ -110,6 +110,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
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#define __io_par(v) __iormb(v)
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#define __iowmb() dma_wmb()
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#define __iomb() dma_mb()
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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@ -17,11 +17,14 @@
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#ifndef __ASSEMBLY__
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#include <linux/refcount.h>
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typedef struct {
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atomic64_t id;
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#ifdef CONFIG_COMPAT
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void *sigpage;
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#endif
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refcount_t pinned;
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void *vdso;
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unsigned long flags;
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} mm_context_t;
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@ -177,7 +177,13 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp)
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#define destroy_context(mm) do { } while(0)
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void check_and_switch_context(struct mm_struct *mm);
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#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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atomic64_set(&mm->context.id, 0);
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refcount_set(&mm->context.pinned, 0);
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return 0;
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}
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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static inline void update_saved_ttbr0(struct task_struct *tsk,
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@ -248,6 +254,9 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
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void verify_cpu_asid_bits(void);
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void post_ttbr_update_workaround(void);
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unsigned long arm64_mm_context_get(struct mm_struct *mm);
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void arm64_mm_context_put(struct mm_struct *mm);
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_MMU_CONTEXT_H */
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@ -1111,6 +1111,7 @@ u64 read_sanitised_ftr_reg(u32 id)
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return 0;
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return regp->sys_val;
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}
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EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
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#define read_sysreg_case(r) \
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case r: return read_sysreg_s(r)
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@ -27,6 +27,10 @@ static DEFINE_PER_CPU(atomic64_t, active_asids);
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static DEFINE_PER_CPU(u64, reserved_asids);
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static cpumask_t tlb_flush_pending;
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static unsigned long max_pinned_asids;
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static unsigned long nr_pinned_asids;
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static unsigned long *pinned_asid_map;
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#define ASID_MASK (~GENMASK(asid_bits - 1, 0))
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#define ASID_FIRST_VERSION (1UL << asid_bits)
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@ -72,7 +76,7 @@ void verify_cpu_asid_bits(void)
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}
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}
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static void set_kpti_asid_bits(void)
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static void set_kpti_asid_bits(unsigned long *map)
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{
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unsigned int len = BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(unsigned long);
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/*
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@ -81,13 +85,15 @@ static void set_kpti_asid_bits(void)
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* is set, then the ASID will map only userspace. Thus
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* mark even as reserved for kernel.
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*/
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memset(asid_map, 0xaa, len);
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memset(map, 0xaa, len);
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}
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static void set_reserved_asid_bits(void)
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{
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if (arm64_kernel_unmapped_at_el0())
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set_kpti_asid_bits();
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if (pinned_asid_map)
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bitmap_copy(asid_map, pinned_asid_map, NUM_USER_ASIDS);
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else if (arm64_kernel_unmapped_at_el0())
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set_kpti_asid_bits(asid_map);
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else
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bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
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}
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@ -165,6 +171,14 @@ static u64 new_context(struct mm_struct *mm)
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if (check_update_reserved_asid(asid, newasid))
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return newasid;
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/*
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* If it is pinned, we can keep using it. Note that reserved
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* takes priority, because even if it is also pinned, we need to
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* update the generation into the reserved_asids.
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*/
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if (refcount_read(&mm->context.pinned))
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return newasid;
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/*
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* We had a valid ASID in a previous life, so try to re-use
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* it if possible.
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@ -256,6 +270,71 @@ switch_mm_fastpath:
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cpu_switch_mm(mm->pgd, mm);
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}
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unsigned long arm64_mm_context_get(struct mm_struct *mm)
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{
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unsigned long flags;
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u64 asid;
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if (!pinned_asid_map)
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return 0;
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raw_spin_lock_irqsave(&cpu_asid_lock, flags);
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asid = atomic64_read(&mm->context.id);
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if (refcount_inc_not_zero(&mm->context.pinned))
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goto out_unlock;
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if (nr_pinned_asids >= max_pinned_asids) {
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asid = 0;
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goto out_unlock;
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}
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if (!asid_gen_match(asid)) {
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/*
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* We went through one or more rollover since that ASID was
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* used. Ensure that it is still valid, or generate a new one.
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*/
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asid = new_context(mm);
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atomic64_set(&mm->context.id, asid);
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}
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nr_pinned_asids++;
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__set_bit(asid2idx(asid), pinned_asid_map);
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refcount_set(&mm->context.pinned, 1);
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out_unlock:
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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asid &= ~ASID_MASK;
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/* Set the equivalent of USER_ASID_BIT */
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if (asid && arm64_kernel_unmapped_at_el0())
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asid |= 1;
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return asid;
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}
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EXPORT_SYMBOL_GPL(arm64_mm_context_get);
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void arm64_mm_context_put(struct mm_struct *mm)
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{
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unsigned long flags;
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u64 asid = atomic64_read(&mm->context.id);
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if (!pinned_asid_map)
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return;
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raw_spin_lock_irqsave(&cpu_asid_lock, flags);
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if (refcount_dec_and_test(&mm->context.pinned)) {
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__clear_bit(asid2idx(asid), pinned_asid_map);
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nr_pinned_asids--;
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}
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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}
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EXPORT_SYMBOL_GPL(arm64_mm_context_put);
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/* Errata workaround post TTBRx_EL1 update. */
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asmlinkage void post_ttbr_update_workaround(void)
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{
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@ -296,8 +375,11 @@ static int asids_update_limit(void)
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{
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unsigned long num_available_asids = NUM_USER_ASIDS;
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if (arm64_kernel_unmapped_at_el0())
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if (arm64_kernel_unmapped_at_el0()) {
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num_available_asids /= 2;
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if (pinned_asid_map)
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set_kpti_asid_bits(pinned_asid_map);
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}
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/*
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* Expect allocation after rollover to fail if we don't have at least
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* one more ASID than CPUs. ASID #0 is reserved for init_mm.
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@ -305,6 +387,13 @@ static int asids_update_limit(void)
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WARN_ON(num_available_asids - 1 <= num_possible_cpus());
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pr_info("ASID allocator initialised with %lu entries\n",
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num_available_asids);
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/*
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* There must always be an ASID available after rollover. Ensure that,
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* even if all CPUs have a reserved ASID and the maximum number of ASIDs
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* are pinned, there still is at least one empty slot in the ASID map.
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*/
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max_pinned_asids = num_available_asids - num_possible_cpus() - 2;
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return 0;
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}
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arch_initcall(asids_update_limit);
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@ -319,13 +408,17 @@ static int asids_init(void)
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panic("Failed to allocate bitmap for %lu ASIDs\n",
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NUM_USER_ASIDS);
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pinned_asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS),
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sizeof(*pinned_asid_map), GFP_KERNEL);
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nr_pinned_asids = 0;
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/*
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* We cannot call set_reserved_asid_bits() here because CPU
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* caps are not finalized yet, so it is safer to assume KPTI
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* and reserve kernel ASID's from beginning.
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*/
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if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0))
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set_kpti_asid_bits();
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set_kpti_asid_bits(asid_map);
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return 0;
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}
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early_initcall(asids_init);
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@ -308,6 +308,16 @@ config ARM_SMMU_V3
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Say Y here if your system includes an IOMMU device implementing
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the ARM SMMUv3 architecture.
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config ARM_SMMU_V3_SVA
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bool "Shared Virtual Addressing support for the ARM SMMUv3"
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depends on ARM_SMMU_V3
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help
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Support for sharing process address spaces with devices using the
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SMMUv3.
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Say Y here if your system supports SVA extensions such as PCIe PASID
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and PRI.
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config S390_IOMMU
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def_bool y if S390 && PCI
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depends on S390 && PCI
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@ -1,2 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
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obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
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arm_smmu_v3-objs-y += arm-smmu-v3.o
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arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
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arm_smmu_v3-objs := $(arm_smmu_v3-objs-y)
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248
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
Normal file
248
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
Normal file
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@ -0,0 +1,248 @@
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|||
// SPDX-License-Identifier: GPL-2.0
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/*
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* Implementation of the IOMMU SVA API for the ARM SMMUv3
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||||
*/
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#include <linux/mm.h>
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#include <linux/mmu_context.h>
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#include <linux/slab.h>
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|
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#include "arm-smmu-v3.h"
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#include "../../io-pgtable-arm.h"
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|
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static DEFINE_MUTEX(sva_lock);
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|
||||
/*
|
||||
* Check if the CPU ASID is available on the SMMU side. If a private context
|
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* descriptor is using it, try to replace it.
|
||||
*/
|
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static struct arm_smmu_ctx_desc *
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arm_smmu_share_asid(struct mm_struct *mm, u16 asid)
|
||||
{
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||||
int ret;
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||||
u32 new_asid;
|
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struct arm_smmu_ctx_desc *cd;
|
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struct arm_smmu_device *smmu;
|
||||
struct arm_smmu_domain *smmu_domain;
|
||||
|
||||
cd = xa_load(&arm_smmu_asid_xa, asid);
|
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if (!cd)
|
||||
return NULL;
|
||||
|
||||
if (cd->mm) {
|
||||
if (WARN_ON(cd->mm != mm))
|
||||
return ERR_PTR(-EINVAL);
|
||||
/* All devices bound to this mm use the same cd struct. */
|
||||
refcount_inc(&cd->refs);
|
||||
return cd;
|
||||
}
|
||||
|
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smmu_domain = container_of(cd, struct arm_smmu_domain, s1_cfg.cd);
|
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smmu = smmu_domain->smmu;
|
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|
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ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd,
|
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XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
|
||||
if (ret)
|
||||
return ERR_PTR(-ENOSPC);
|
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/*
|
||||
* Race with unmap: TLB invalidations will start targeting the new ASID,
|
||||
* which isn't assigned yet. We'll do an invalidate-all on the old ASID
|
||||
* later, so it doesn't matter.
|
||||
*/
|
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cd->asid = new_asid;
|
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/*
|
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* Update ASID and invalidate CD in all associated masters. There will
|
||||
* be some overlap between use of both ASIDs, until we invalidate the
|
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* TLB.
|
||||
*/
|
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arm_smmu_write_ctx_desc(smmu_domain, 0, cd);
|
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|
||||
/* Invalidate TLB entries previously associated with that context */
|
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arm_smmu_tlb_inv_asid(smmu, asid);
|
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|
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xa_erase(&arm_smmu_asid_xa, asid);
|
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return NULL;
|
||||
}
|
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|
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__maybe_unused
|
||||
static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
|
||||
{
|
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u16 asid;
|
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int err = 0;
|
||||
u64 tcr, par, reg;
|
||||
struct arm_smmu_ctx_desc *cd;
|
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struct arm_smmu_ctx_desc *ret = NULL;
|
||||
|
||||
asid = arm64_mm_context_get(mm);
|
||||
if (!asid)
|
||||
return ERR_PTR(-ESRCH);
|
||||
|
||||
cd = kzalloc(sizeof(*cd), GFP_KERNEL);
|
||||
if (!cd) {
|
||||
err = -ENOMEM;
|
||||
goto out_put_context;
|
||||
}
|
||||
|
||||
refcount_set(&cd->refs, 1);
|
||||
|
||||
mutex_lock(&arm_smmu_asid_lock);
|
||||
ret = arm_smmu_share_asid(mm, asid);
|
||||
if (ret) {
|
||||
mutex_unlock(&arm_smmu_asid_lock);
|
||||
goto out_free_cd;
|
||||
}
|
||||
|
||||
err = xa_insert(&arm_smmu_asid_xa, asid, cd, GFP_KERNEL);
|
||||
mutex_unlock(&arm_smmu_asid_lock);
|
||||
|
||||
if (err)
|
||||
goto out_free_asid;
|
||||
|
||||
tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - vabits_actual) |
|
||||
FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
|
||||
FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
|
||||
FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
|
||||
CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
|
||||
|
||||
switch (PAGE_SIZE) {
|
||||
case SZ_4K:
|
||||
tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K);
|
||||
break;
|
||||
case SZ_16K:
|
||||
tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K);
|
||||
break;
|
||||
case SZ_64K:
|
||||
tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K);
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
err = -EINVAL;
|
||||
goto out_free_asid;
|
||||
}
|
||||
|
||||
reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
|
||||
par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
|
||||
tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
|
||||
|
||||
cd->ttbr = virt_to_phys(mm->pgd);
|
||||
cd->tcr = tcr;
|
||||
/*
|
||||
* MAIR value is pretty much constant and global, so we can just get it
|
||||
* from the current CPU register
|
||||
*/
|
||||
cd->mair = read_sysreg(mair_el1);
|
||||
cd->asid = asid;
|
||||
cd->mm = mm;
|
||||
|
||||
return cd;
|
||||
|
||||
out_free_asid:
|
||||
arm_smmu_free_asid(cd);
|
||||
out_free_cd:
|
||||
kfree(cd);
|
||||
out_put_context:
|
||||
arm64_mm_context_put(mm);
|
||||
return err < 0 ? ERR_PTR(err) : ret;
|
||||
}
|
||||
|
||||
__maybe_unused
|
||||
static void arm_smmu_free_shared_cd(struct arm_smmu_ctx_desc *cd)
|
||||
{
|
||||
if (arm_smmu_free_asid(cd)) {
|
||||
/* Unpin ASID */
|
||||
arm64_mm_context_put(cd->mm);
|
||||
kfree(cd);
|
||||
}
|
||||
}
|
||||
|
||||
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
|
||||
{
|
||||
unsigned long reg, fld;
|
||||
unsigned long oas;
|
||||
unsigned long asid_bits;
|
||||
u32 feat_mask = ARM_SMMU_FEAT_BTM | ARM_SMMU_FEAT_COHERENCY;
|
||||
|
||||
if (vabits_actual == 52)
|
||||
feat_mask |= ARM_SMMU_FEAT_VAX;
|
||||
|
||||
if ((smmu->features & feat_mask) != feat_mask)
|
||||
return false;
|
||||
|
||||
if (!(smmu->pgsize_bitmap & PAGE_SIZE))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Get the smallest PA size of all CPUs (sanitized by cpufeature). We're
|
||||
* not even pretending to support AArch32 here. Abort if the MMU outputs
|
||||
* addresses larger than what we support.
|
||||
*/
|
||||
reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
|
||||
fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
|
||||
oas = id_aa64mmfr0_parange_to_phys_shift(fld);
|
||||
if (smmu->oas < oas)
|
||||
return false;
|
||||
|
||||
/* We can support bigger ASIDs than the CPU, but not smaller */
|
||||
fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_ASID_SHIFT);
|
||||
asid_bits = fld ? 16 : 8;
|
||||
if (smmu->asid_bits < asid_bits)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* See max_pinned_asids in arch/arm64/mm/context.c. The following is
|
||||
* generally the maximum number of bindable processes.
|
||||
*/
|
||||
if (arm64_kernel_unmapped_at_el0())
|
||||
asid_bits--;
|
||||
dev_dbg(smmu->dev, "%d shared contexts\n", (1 << asid_bits) -
|
||||
num_possible_cpus() - 2);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool arm_smmu_iopf_supported(struct arm_smmu_master *master)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool arm_smmu_master_sva_supported(struct arm_smmu_master *master)
|
||||
{
|
||||
if (!(master->smmu->features & ARM_SMMU_FEAT_SVA))
|
||||
return false;
|
||||
|
||||
/* SSID and IOPF support are mandatory for the moment */
|
||||
return master->ssid_bits && arm_smmu_iopf_supported(master);
|
||||
}
|
||||
|
||||
bool arm_smmu_master_sva_enabled(struct arm_smmu_master *master)
|
||||
{
|
||||
bool enabled;
|
||||
|
||||
mutex_lock(&sva_lock);
|
||||
enabled = master->sva_enabled;
|
||||
mutex_unlock(&sva_lock);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
int arm_smmu_master_enable_sva(struct arm_smmu_master *master)
|
||||
{
|
||||
mutex_lock(&sva_lock);
|
||||
master->sva_enabled = true;
|
||||
mutex_unlock(&sva_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_smmu_master_disable_sva(struct arm_smmu_master *master)
|
||||
{
|
||||
mutex_lock(&sva_lock);
|
||||
if (!list_empty(&master->bonds)) {
|
||||
dev_err(master->dev, "cannot disable SVA, device is bound\n");
|
||||
mutex_unlock(&sva_lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
master->sva_enabled = false;
|
||||
mutex_unlock(&sva_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
723
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
Normal file
723
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
Normal file
|
|
@ -0,0 +1,723 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* IOMMU API for ARM architected SMMUv3 implementations.
|
||||
*
|
||||
* Copyright (C) 2015 ARM Limited
|
||||
*/
|
||||
|
||||
#ifndef _ARM_SMMU_V3_H
|
||||
#define _ARM_SMMU_V3_H
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/iommu.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mmzone.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
/* MMIO registers */
|
||||
#define ARM_SMMU_IDR0 0x0
|
||||
#define IDR0_ST_LVL GENMASK(28, 27)
|
||||
#define IDR0_ST_LVL_2LVL 1
|
||||
#define IDR0_STALL_MODEL GENMASK(25, 24)
|
||||
#define IDR0_STALL_MODEL_STALL 0
|
||||
#define IDR0_STALL_MODEL_FORCE 2
|
||||
#define IDR0_TTENDIAN GENMASK(22, 21)
|
||||
#define IDR0_TTENDIAN_MIXED 0
|
||||
#define IDR0_TTENDIAN_LE 2
|
||||
#define IDR0_TTENDIAN_BE 3
|
||||
#define IDR0_CD2L (1 << 19)
|
||||
#define IDR0_VMID16 (1 << 18)
|
||||
#define IDR0_PRI (1 << 16)
|
||||
#define IDR0_SEV (1 << 14)
|
||||
#define IDR0_MSI (1 << 13)
|
||||
#define IDR0_ASID16 (1 << 12)
|
||||
#define IDR0_ATS (1 << 10)
|
||||
#define IDR0_HYP (1 << 9)
|
||||
#define IDR0_COHACC (1 << 4)
|
||||
#define IDR0_TTF GENMASK(3, 2)
|
||||
#define IDR0_TTF_AARCH64 2
|
||||
#define IDR0_TTF_AARCH32_64 3
|
||||
#define IDR0_S1P (1 << 1)
|
||||
#define IDR0_S2P (1 << 0)
|
||||
|
||||
#define ARM_SMMU_IDR1 0x4
|
||||
#define IDR1_TABLES_PRESET (1 << 30)
|
||||
#define IDR1_QUEUES_PRESET (1 << 29)
|
||||
#define IDR1_REL (1 << 28)
|
||||
#define IDR1_CMDQS GENMASK(25, 21)
|
||||
#define IDR1_EVTQS GENMASK(20, 16)
|
||||
#define IDR1_PRIQS GENMASK(15, 11)
|
||||
#define IDR1_SSIDSIZE GENMASK(10, 6)
|
||||
#define IDR1_SIDSIZE GENMASK(5, 0)
|
||||
|
||||
#define ARM_SMMU_IDR3 0xc
|
||||
#define IDR3_RIL (1 << 10)
|
||||
|
||||
#define ARM_SMMU_IDR5 0x14
|
||||
#define IDR5_STALL_MAX GENMASK(31, 16)
|
||||
#define IDR5_GRAN64K (1 << 6)
|
||||
#define IDR5_GRAN16K (1 << 5)
|
||||
#define IDR5_GRAN4K (1 << 4)
|
||||
#define IDR5_OAS GENMASK(2, 0)
|
||||
#define IDR5_OAS_32_BIT 0
|
||||
#define IDR5_OAS_36_BIT 1
|
||||
#define IDR5_OAS_40_BIT 2
|
||||
#define IDR5_OAS_42_BIT 3
|
||||
#define IDR5_OAS_44_BIT 4
|
||||
#define IDR5_OAS_48_BIT 5
|
||||
#define IDR5_OAS_52_BIT 6
|
||||
#define IDR5_VAX GENMASK(11, 10)
|
||||
#define IDR5_VAX_52_BIT 1
|
||||
|
||||
#define ARM_SMMU_CR0 0x20
|
||||
#define CR0_ATSCHK (1 << 4)
|
||||
#define CR0_CMDQEN (1 << 3)
|
||||
#define CR0_EVTQEN (1 << 2)
|
||||
#define CR0_PRIQEN (1 << 1)
|
||||
#define CR0_SMMUEN (1 << 0)
|
||||
|
||||
#define ARM_SMMU_CR0ACK 0x24
|
||||
|
||||
#define ARM_SMMU_CR1 0x28
|
||||
#define CR1_TABLE_SH GENMASK(11, 10)
|
||||
#define CR1_TABLE_OC GENMASK(9, 8)
|
||||
#define CR1_TABLE_IC GENMASK(7, 6)
|
||||
#define CR1_QUEUE_SH GENMASK(5, 4)
|
||||
#define CR1_QUEUE_OC GENMASK(3, 2)
|
||||
#define CR1_QUEUE_IC GENMASK(1, 0)
|
||||
/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
|
||||
#define CR1_CACHE_NC 0
|
||||
#define CR1_CACHE_WB 1
|
||||
#define CR1_CACHE_WT 2
|
||||
|
||||
#define ARM_SMMU_CR2 0x2c
|
||||
#define CR2_PTM (1 << 2)
|
||||
#define CR2_RECINVSID (1 << 1)
|
||||
#define CR2_E2H (1 << 0)
|
||||
|
||||
#define ARM_SMMU_GBPA 0x44
|
||||
#define GBPA_UPDATE (1 << 31)
|
||||
#define GBPA_ABORT (1 << 20)
|
||||
|
||||
#define ARM_SMMU_IRQ_CTRL 0x50
|
||||
#define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
|
||||
#define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
|
||||
#define IRQ_CTRL_GERROR_IRQEN (1 << 0)
|
||||
|
||||
#define ARM_SMMU_IRQ_CTRLACK 0x54
|
||||
|
||||
#define ARM_SMMU_GERROR 0x60
|
||||
#define GERROR_SFM_ERR (1 << 8)
|
||||
#define GERROR_MSI_GERROR_ABT_ERR (1 << 7)
|
||||
#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6)
|
||||
#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5)
|
||||
#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4)
|
||||
#define GERROR_PRIQ_ABT_ERR (1 << 3)
|
||||
#define GERROR_EVTQ_ABT_ERR (1 << 2)
|
||||
#define GERROR_CMDQ_ERR (1 << 0)
|
||||
#define GERROR_ERR_MASK 0xfd
|
||||
|
||||
#define ARM_SMMU_GERRORN 0x64
|
||||
|
||||
#define ARM_SMMU_GERROR_IRQ_CFG0 0x68
|
||||
#define ARM_SMMU_GERROR_IRQ_CFG1 0x70
|
||||
#define ARM_SMMU_GERROR_IRQ_CFG2 0x74
|
||||
|
||||
#define ARM_SMMU_STRTAB_BASE 0x80
|
||||
#define STRTAB_BASE_RA (1UL << 62)
|
||||
#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
|
||||
|
||||
#define ARM_SMMU_STRTAB_BASE_CFG 0x88
|
||||
#define STRTAB_BASE_CFG_FMT GENMASK(17, 16)
|
||||
#define STRTAB_BASE_CFG_FMT_LINEAR 0
|
||||
#define STRTAB_BASE_CFG_FMT_2LVL 1
|
||||
#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6)
|
||||
#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0)
|
||||
|
||||
#define ARM_SMMU_CMDQ_BASE 0x90
|
||||
#define ARM_SMMU_CMDQ_PROD 0x98
|
||||
#define ARM_SMMU_CMDQ_CONS 0x9c
|
||||
|
||||
#define ARM_SMMU_EVTQ_BASE 0xa0
|
||||
#define ARM_SMMU_EVTQ_PROD 0x100a8
|
||||
#define ARM_SMMU_EVTQ_CONS 0x100ac
|
||||
#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0
|
||||
#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8
|
||||
#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc
|
||||
|
||||
#define ARM_SMMU_PRIQ_BASE 0xc0
|
||||
#define ARM_SMMU_PRIQ_PROD 0x100c8
|
||||
#define ARM_SMMU_PRIQ_CONS 0x100cc
|
||||
#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0
|
||||
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
|
||||
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
|
||||
|
||||
#define ARM_SMMU_REG_SZ 0xe00
|
||||
|
||||
/* Common MSI config fields */
|
||||
#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
|
||||
#define MSI_CFG2_SH GENMASK(5, 4)
|
||||
#define MSI_CFG2_MEMATTR GENMASK(3, 0)
|
||||
|
||||
/* Common memory attribute values */
|
||||
#define ARM_SMMU_SH_NSH 0
|
||||
#define ARM_SMMU_SH_OSH 2
|
||||
#define ARM_SMMU_SH_ISH 3
|
||||
#define ARM_SMMU_MEMATTR_DEVICE_nGnRE 0x1
|
||||
#define ARM_SMMU_MEMATTR_OIWB 0xf
|
||||
|
||||
#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
|
||||
#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
|
||||
#define Q_OVERFLOW_FLAG (1U << 31)
|
||||
#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG)
|
||||
#define Q_ENT(q, p) ((q)->base + \
|
||||
Q_IDX(&((q)->llq), p) * \
|
||||
(q)->ent_dwords)
|
||||
|
||||
#define Q_BASE_RWA (1UL << 62)
|
||||
#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
|
||||
#define Q_BASE_LOG2SIZE GENMASK(4, 0)
|
||||
|
||||
/* Ensure DMA allocations are naturally aligned */
|
||||
#ifdef CONFIG_CMA_ALIGNMENT
|
||||
#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + CONFIG_CMA_ALIGNMENT)
|
||||
#else
|
||||
#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Stream table.
|
||||
*
|
||||
* Linear: Enough to cover 1 << IDR1.SIDSIZE entries
|
||||
* 2lvl: 128k L1 entries,
|
||||
* 256 lazy entries per table (each table covers a PCI bus)
|
||||
*/
|
||||
#define STRTAB_L1_SZ_SHIFT 20
|
||||
#define STRTAB_SPLIT 8
|
||||
|
||||
#define STRTAB_L1_DESC_DWORDS 1
|
||||
#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
|
||||
#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
|
||||
|
||||
#define STRTAB_STE_DWORDS 8
|
||||
#define STRTAB_STE_0_V (1UL << 0)
|
||||
#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
|
||||
#define STRTAB_STE_0_CFG_ABORT 0
|
||||
#define STRTAB_STE_0_CFG_BYPASS 4
|
||||
#define STRTAB_STE_0_CFG_S1_TRANS 5
|
||||
#define STRTAB_STE_0_CFG_S2_TRANS 6
|
||||
|
||||
#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
|
||||
#define STRTAB_STE_0_S1FMT_LINEAR 0
|
||||
#define STRTAB_STE_0_S1FMT_64K_L2 2
|
||||
#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
|
||||
#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
|
||||
|
||||
#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
|
||||
#define STRTAB_STE_1_S1DSS_TERMINATE 0x0
|
||||
#define STRTAB_STE_1_S1DSS_BYPASS 0x1
|
||||
#define STRTAB_STE_1_S1DSS_SSID0 0x2
|
||||
|
||||
#define STRTAB_STE_1_S1C_CACHE_NC 0UL
|
||||
#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
|
||||
#define STRTAB_STE_1_S1C_CACHE_WT 2UL
|
||||
#define STRTAB_STE_1_S1C_CACHE_WB 3UL
|
||||
#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2)
|
||||
#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4)
|
||||
#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6)
|
||||
|
||||
#define STRTAB_STE_1_S1STALLD (1UL << 27)
|
||||
|
||||
#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28)
|
||||
#define STRTAB_STE_1_EATS_ABT 0UL
|
||||
#define STRTAB_STE_1_EATS_TRANS 1UL
|
||||
#define STRTAB_STE_1_EATS_S1CHK 2UL
|
||||
|
||||
#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30)
|
||||
#define STRTAB_STE_1_STRW_NSEL1 0UL
|
||||
#define STRTAB_STE_1_STRW_EL2 2UL
|
||||
|
||||
#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44)
|
||||
#define STRTAB_STE_1_SHCFG_INCOMING 1UL
|
||||
|
||||
#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0)
|
||||
#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
|
||||
#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0)
|
||||
#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6)
|
||||
#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8)
|
||||
#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10)
|
||||
#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12)
|
||||
#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14)
|
||||
#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16)
|
||||
#define STRTAB_STE_2_S2AA64 (1UL << 51)
|
||||
#define STRTAB_STE_2_S2ENDI (1UL << 52)
|
||||
#define STRTAB_STE_2_S2PTW (1UL << 54)
|
||||
#define STRTAB_STE_2_S2R (1UL << 58)
|
||||
|
||||
#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
|
||||
|
||||
/*
|
||||
* Context descriptors.
|
||||
*
|
||||
* Linear: when less than 1024 SSIDs are supported
|
||||
* 2lvl: at most 1024 L1 entries,
|
||||
* 1024 lazy entries per table.
|
||||
*/
|
||||
#define CTXDESC_SPLIT 10
|
||||
#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT)
|
||||
|
||||
#define CTXDESC_L1_DESC_DWORDS 1
|
||||
#define CTXDESC_L1_DESC_V (1UL << 0)
|
||||
#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
|
||||
|
||||
#define CTXDESC_CD_DWORDS 8
|
||||
#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
|
||||
#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
|
||||
#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
|
||||
#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
|
||||
#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12)
|
||||
#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14)
|
||||
#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30)
|
||||
|
||||
#define CTXDESC_CD_0_ENDI (1UL << 15)
|
||||
#define CTXDESC_CD_0_V (1UL << 31)
|
||||
|
||||
#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
|
||||
#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38)
|
||||
|
||||
#define CTXDESC_CD_0_AA64 (1UL << 41)
|
||||
#define CTXDESC_CD_0_S (1UL << 44)
|
||||
#define CTXDESC_CD_0_R (1UL << 45)
|
||||
#define CTXDESC_CD_0_A (1UL << 46)
|
||||
#define CTXDESC_CD_0_ASET (1UL << 47)
|
||||
#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
|
||||
|
||||
#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
|
||||
|
||||
/*
|
||||
* When the SMMU only supports linear context descriptor tables, pick a
|
||||
* reasonable size limit (64kB).
|
||||
*/
|
||||
#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3))
|
||||
|
||||
/* Command queue */
|
||||
#define CMDQ_ENT_SZ_SHIFT 4
|
||||
#define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3)
|
||||
#define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
|
||||
|
||||
#define CMDQ_CONS_ERR GENMASK(30, 24)
|
||||
#define CMDQ_ERR_CERROR_NONE_IDX 0
|
||||
#define CMDQ_ERR_CERROR_ILL_IDX 1
|
||||
#define CMDQ_ERR_CERROR_ABT_IDX 2
|
||||
#define CMDQ_ERR_CERROR_ATC_INV_IDX 3
|
||||
|
||||
#define CMDQ_PROD_OWNED_FLAG Q_OVERFLOW_FLAG
|
||||
|
||||
/*
|
||||
* This is used to size the command queue and therefore must be at least
|
||||
* BITS_PER_LONG so that the valid_map works correctly (it relies on the
|
||||
* total number of queue entries being a multiple of BITS_PER_LONG).
|
||||
*/
|
||||
#define CMDQ_BATCH_ENTRIES BITS_PER_LONG
|
||||
|
||||
#define CMDQ_0_OP GENMASK_ULL(7, 0)
|
||||
#define CMDQ_0_SSV (1UL << 11)
|
||||
|
||||
#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32)
|
||||
#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0)
|
||||
#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
|
||||
|
||||
#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12)
|
||||
#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)
|
||||
#define CMDQ_CFGI_1_LEAF (1UL << 0)
|
||||
#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)
|
||||
|
||||
#define CMDQ_TLBI_0_NUM GENMASK_ULL(16, 12)
|
||||
#define CMDQ_TLBI_RANGE_NUM_MAX 31
|
||||
#define CMDQ_TLBI_0_SCALE GENMASK_ULL(24, 20)
|
||||
#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)
|
||||
#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)
|
||||
#define CMDQ_TLBI_1_LEAF (1UL << 0)
|
||||
#define CMDQ_TLBI_1_TTL GENMASK_ULL(9, 8)
|
||||
#define CMDQ_TLBI_1_TG GENMASK_ULL(11, 10)
|
||||
#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
|
||||
#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
|
||||
|
||||
#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12)
|
||||
#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)
|
||||
#define CMDQ_ATC_0_GLOBAL (1UL << 9)
|
||||
#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0)
|
||||
#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)
|
||||
|
||||
#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12)
|
||||
#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)
|
||||
#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0)
|
||||
#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12)
|
||||
|
||||
#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12)
|
||||
#define CMDQ_SYNC_0_CS_NONE 0
|
||||
#define CMDQ_SYNC_0_CS_IRQ 1
|
||||
#define CMDQ_SYNC_0_CS_SEV 2
|
||||
#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22)
|
||||
#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24)
|
||||
#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32)
|
||||
#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
|
||||
|
||||
/* Event queue */
|
||||
#define EVTQ_ENT_SZ_SHIFT 5
|
||||
#define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3)
|
||||
#define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
|
||||
|
||||
#define EVTQ_0_ID GENMASK_ULL(7, 0)
|
||||
|
||||
/* PRI queue */
|
||||
#define PRIQ_ENT_SZ_SHIFT 4
|
||||
#define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3)
|
||||
#define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
|
||||
|
||||
#define PRIQ_0_SID GENMASK_ULL(31, 0)
|
||||
#define PRIQ_0_SSID GENMASK_ULL(51, 32)
|
||||
#define PRIQ_0_PERM_PRIV (1UL << 58)
|
||||
#define PRIQ_0_PERM_EXEC (1UL << 59)
|
||||
#define PRIQ_0_PERM_READ (1UL << 60)
|
||||
#define PRIQ_0_PERM_WRITE (1UL << 61)
|
||||
#define PRIQ_0_PRG_LAST (1UL << 62)
|
||||
#define PRIQ_0_SSID_V (1UL << 63)
|
||||
|
||||
#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0)
|
||||
#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)
|
||||
|
||||
/* High-level queue structures */
|
||||
#define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */
|
||||
#define ARM_SMMU_POLL_SPIN_COUNT 10
|
||||
|
||||
#define MSI_IOVA_BASE 0x8000000
|
||||
#define MSI_IOVA_LENGTH 0x100000
|
||||
|
||||
enum pri_resp {
|
||||
PRI_RESP_DENY = 0,
|
||||
PRI_RESP_FAIL = 1,
|
||||
PRI_RESP_SUCC = 2,
|
||||
};
|
||||
|
||||
struct arm_smmu_cmdq_ent {
|
||||
/* Common fields */
|
||||
u8 opcode;
|
||||
bool substream_valid;
|
||||
|
||||
/* Command-specific fields */
|
||||
union {
|
||||
#define CMDQ_OP_PREFETCH_CFG 0x1
|
||||
struct {
|
||||
u32 sid;
|
||||
u8 size;
|
||||
u64 addr;
|
||||
} prefetch;
|
||||
|
||||
#define CMDQ_OP_CFGI_STE 0x3
|
||||
#define CMDQ_OP_CFGI_ALL 0x4
|
||||
#define CMDQ_OP_CFGI_CD 0x5
|
||||
#define CMDQ_OP_CFGI_CD_ALL 0x6
|
||||
struct {
|
||||
u32 sid;
|
||||
u32 ssid;
|
||||
union {
|
||||
bool leaf;
|
||||
u8 span;
|
||||
};
|
||||
} cfgi;
|
||||
|
||||
#define CMDQ_OP_TLBI_NH_ASID 0x11
|
||||
#define CMDQ_OP_TLBI_NH_VA 0x12
|
||||
#define CMDQ_OP_TLBI_EL2_ALL 0x20
|
||||
#define CMDQ_OP_TLBI_S12_VMALL 0x28
|
||||
#define CMDQ_OP_TLBI_S2_IPA 0x2a
|
||||
#define CMDQ_OP_TLBI_NSNH_ALL 0x30
|
||||
struct {
|
||||
u8 num;
|
||||
u8 scale;
|
||||
u16 asid;
|
||||
u16 vmid;
|
||||
bool leaf;
|
||||
u8 ttl;
|
||||
u8 tg;
|
||||
u64 addr;
|
||||
} tlbi;
|
||||
|
||||
#define CMDQ_OP_ATC_INV 0x40
|
||||
#define ATC_INV_SIZE_ALL 52
|
||||
struct {
|
||||
u32 sid;
|
||||
u32 ssid;
|
||||
u64 addr;
|
||||
u8 size;
|
||||
bool global;
|
||||
} atc;
|
||||
|
||||
#define CMDQ_OP_PRI_RESP 0x41
|
||||
struct {
|
||||
u32 sid;
|
||||
u32 ssid;
|
||||
u16 grpid;
|
||||
enum pri_resp resp;
|
||||
} pri;
|
||||
|
||||
#define CMDQ_OP_CMD_SYNC 0x46
|
||||
struct {
|
||||
u64 msiaddr;
|
||||
} sync;
|
||||
};
|
||||
};
|
||||
|
||||
struct arm_smmu_ll_queue {
|
||||
union {
|
||||
u64 val;
|
||||
struct {
|
||||
u32 prod;
|
||||
u32 cons;
|
||||
};
|
||||
struct {
|
||||
atomic_t prod;
|
||||
atomic_t cons;
|
||||
} atomic;
|
||||
u8 __pad[SMP_CACHE_BYTES];
|
||||
} ____cacheline_aligned_in_smp;
|
||||
u32 max_n_shift;
|
||||
};
|
||||
|
||||
struct arm_smmu_queue {
|
||||
struct arm_smmu_ll_queue llq;
|
||||
int irq; /* Wired interrupt */
|
||||
|
||||
__le64 *base;
|
||||
dma_addr_t base_dma;
|
||||
u64 q_base;
|
||||
|
||||
size_t ent_dwords;
|
||||
|
||||
u32 __iomem *prod_reg;
|
||||
u32 __iomem *cons_reg;
|
||||
};
|
||||
|
||||
struct arm_smmu_queue_poll {
|
||||
ktime_t timeout;
|
||||
unsigned int delay;
|
||||
unsigned int spin_cnt;
|
||||
bool wfe;
|
||||
};
|
||||
|
||||
struct arm_smmu_cmdq {
|
||||
struct arm_smmu_queue q;
|
||||
atomic_long_t *valid_map;
|
||||
atomic_t owner_prod;
|
||||
atomic_t lock;
|
||||
};
|
||||
|
||||
struct arm_smmu_cmdq_batch {
|
||||
u64 cmds[CMDQ_BATCH_ENTRIES * CMDQ_ENT_DWORDS];
|
||||
int num;
|
||||
};
|
||||
|
||||
struct arm_smmu_evtq {
|
||||
struct arm_smmu_queue q;
|
||||
u32 max_stalls;
|
||||
};
|
||||
|
||||
struct arm_smmu_priq {
|
||||
struct arm_smmu_queue q;
|
||||
};
|
||||
|
||||
/* High-level stream table and context descriptor structures */
|
||||
struct arm_smmu_strtab_l1_desc {
|
||||
u8 span;
|
||||
|
||||
__le64 *l2ptr;
|
||||
dma_addr_t l2ptr_dma;
|
||||
};
|
||||
|
||||
struct arm_smmu_ctx_desc {
|
||||
u16 asid;
|
||||
u64 ttbr;
|
||||
u64 tcr;
|
||||
u64 mair;
|
||||
|
||||
refcount_t refs;
|
||||
struct mm_struct *mm;
|
||||
};
|
||||
|
||||
struct arm_smmu_l1_ctx_desc {
|
||||
__le64 *l2ptr;
|
||||
dma_addr_t l2ptr_dma;
|
||||
};
|
||||
|
||||
struct arm_smmu_ctx_desc_cfg {
|
||||
__le64 *cdtab;
|
||||
dma_addr_t cdtab_dma;
|
||||
struct arm_smmu_l1_ctx_desc *l1_desc;
|
||||
unsigned int num_l1_ents;
|
||||
};
|
||||
|
||||
struct arm_smmu_s1_cfg {
|
||||
struct arm_smmu_ctx_desc_cfg cdcfg;
|
||||
struct arm_smmu_ctx_desc cd;
|
||||
u8 s1fmt;
|
||||
u8 s1cdmax;
|
||||
};
|
||||
|
||||
struct arm_smmu_s2_cfg {
|
||||
u16 vmid;
|
||||
u64 vttbr;
|
||||
u64 vtcr;
|
||||
};
|
||||
|
||||
struct arm_smmu_strtab_cfg {
|
||||
__le64 *strtab;
|
||||
dma_addr_t strtab_dma;
|
||||
struct arm_smmu_strtab_l1_desc *l1_desc;
|
||||
unsigned int num_l1_ents;
|
||||
|
||||
u64 strtab_base;
|
||||
u32 strtab_base_cfg;
|
||||
};
|
||||
|
||||
/* An SMMUv3 instance */
|
||||
struct arm_smmu_device {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
void __iomem *page1;
|
||||
|
||||
#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
|
||||
#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
|
||||
#define ARM_SMMU_FEAT_TT_LE (1 << 2)
|
||||
#define ARM_SMMU_FEAT_TT_BE (1 << 3)
|
||||
#define ARM_SMMU_FEAT_PRI (1 << 4)
|
||||
#define ARM_SMMU_FEAT_ATS (1 << 5)
|
||||
#define ARM_SMMU_FEAT_SEV (1 << 6)
|
||||
#define ARM_SMMU_FEAT_MSI (1 << 7)
|
||||
#define ARM_SMMU_FEAT_COHERENCY (1 << 8)
|
||||
#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9)
|
||||
#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10)
|
||||
#define ARM_SMMU_FEAT_STALLS (1 << 11)
|
||||
#define ARM_SMMU_FEAT_HYP (1 << 12)
|
||||
#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13)
|
||||
#define ARM_SMMU_FEAT_VAX (1 << 14)
|
||||
#define ARM_SMMU_FEAT_RANGE_INV (1 << 15)
|
||||
#define ARM_SMMU_FEAT_BTM (1 << 16)
|
||||
#define ARM_SMMU_FEAT_SVA (1 << 17)
|
||||
u32 features;
|
||||
|
||||
#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
|
||||
#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1)
|
||||
#define ARM_SMMU_OPT_MSIPOLL (1 << 2)
|
||||
u32 options;
|
||||
|
||||
struct arm_smmu_cmdq cmdq;
|
||||
struct arm_smmu_evtq evtq;
|
||||
struct arm_smmu_priq priq;
|
||||
|
||||
int gerr_irq;
|
||||
int combined_irq;
|
||||
|
||||
unsigned long ias; /* IPA */
|
||||
unsigned long oas; /* PA */
|
||||
unsigned long pgsize_bitmap;
|
||||
|
||||
#define ARM_SMMU_MAX_ASIDS (1 << 16)
|
||||
unsigned int asid_bits;
|
||||
|
||||
#define ARM_SMMU_MAX_VMIDS (1 << 16)
|
||||
unsigned int vmid_bits;
|
||||
DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS);
|
||||
|
||||
unsigned int ssid_bits;
|
||||
unsigned int sid_bits;
|
||||
|
||||
struct arm_smmu_strtab_cfg strtab_cfg;
|
||||
|
||||
/* IOMMU core code handle */
|
||||
struct iommu_device iommu;
|
||||
};
|
||||
|
||||
/* SMMU private data for each master */
|
||||
struct arm_smmu_master {
|
||||
struct arm_smmu_device *smmu;
|
||||
struct device *dev;
|
||||
struct arm_smmu_domain *domain;
|
||||
struct list_head domain_head;
|
||||
u32 *sids;
|
||||
unsigned int num_sids;
|
||||
bool ats_enabled;
|
||||
bool sva_enabled;
|
||||
struct list_head bonds;
|
||||
unsigned int ssid_bits;
|
||||
};
|
||||
|
||||
/* SMMU private data for an IOMMU domain */
|
||||
enum arm_smmu_domain_stage {
|
||||
ARM_SMMU_DOMAIN_S1 = 0,
|
||||
ARM_SMMU_DOMAIN_S2,
|
||||
ARM_SMMU_DOMAIN_NESTED,
|
||||
ARM_SMMU_DOMAIN_BYPASS,
|
||||
};
|
||||
|
||||
struct arm_smmu_domain {
|
||||
struct arm_smmu_device *smmu;
|
||||
struct mutex init_mutex; /* Protects smmu pointer */
|
||||
|
||||
struct io_pgtable_ops *pgtbl_ops;
|
||||
bool non_strict;
|
||||
atomic_t nr_ats_masters;
|
||||
|
||||
enum arm_smmu_domain_stage stage;
|
||||
union {
|
||||
struct arm_smmu_s1_cfg s1_cfg;
|
||||
struct arm_smmu_s2_cfg s2_cfg;
|
||||
};
|
||||
|
||||
struct iommu_domain domain;
|
||||
|
||||
struct list_head devices;
|
||||
spinlock_t devices_lock;
|
||||
};
|
||||
|
||||
extern struct xarray arm_smmu_asid_xa;
|
||||
extern struct mutex arm_smmu_asid_lock;
|
||||
|
||||
int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid,
|
||||
struct arm_smmu_ctx_desc *cd);
|
||||
void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid);
|
||||
bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd);
|
||||
|
||||
#ifdef CONFIG_ARM_SMMU_V3_SVA
|
||||
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
|
||||
bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);
|
||||
bool arm_smmu_master_sva_enabled(struct arm_smmu_master *master);
|
||||
int arm_smmu_master_enable_sva(struct arm_smmu_master *master);
|
||||
int arm_smmu_master_disable_sva(struct arm_smmu_master *master);
|
||||
#else /* CONFIG_ARM_SMMU_V3_SVA */
|
||||
static inline bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool arm_smmu_master_sva_supported(struct arm_smmu_master *master)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool arm_smmu_master_sva_enabled(struct arm_smmu_master *master)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int arm_smmu_master_enable_sva(struct arm_smmu_master *master)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int arm_smmu_master_disable_sva(struct arm_smmu_master *master)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_ARM_SMMU_V3_SVA */
|
||||
#endif /* _ARM_SMMU_V3_H */
|
||||
|
|
@ -68,7 +68,8 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cavium_init_context(struct arm_smmu_domain *smmu_domain)
|
||||
static int cavium_init_context(struct arm_smmu_domain *smmu_domain,
|
||||
struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
|
||||
{
|
||||
struct cavium_smmu *cs = container_of(smmu_domain->smmu,
|
||||
struct cavium_smmu, smmu);
|
||||
|
|
|
|||
|
|
@ -65,41 +65,10 @@ module_param(disable_bypass, bool, S_IRUGO);
|
|||
MODULE_PARM_DESC(disable_bypass,
|
||||
"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
|
||||
|
||||
struct arm_smmu_s2cr {
|
||||
struct iommu_group *group;
|
||||
int count;
|
||||
enum arm_smmu_s2cr_type type;
|
||||
enum arm_smmu_s2cr_privcfg privcfg;
|
||||
u8 cbndx;
|
||||
};
|
||||
|
||||
#define s2cr_init_val (struct arm_smmu_s2cr){ \
|
||||
.type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \
|
||||
}
|
||||
|
||||
struct arm_smmu_smr {
|
||||
u16 mask;
|
||||
u16 id;
|
||||
bool valid;
|
||||
};
|
||||
|
||||
struct arm_smmu_cb {
|
||||
u64 ttbr[2];
|
||||
u32 tcr[2];
|
||||
u32 mair[2];
|
||||
struct arm_smmu_cfg *cfg;
|
||||
};
|
||||
|
||||
struct arm_smmu_master_cfg {
|
||||
struct arm_smmu_device *smmu;
|
||||
s16 smendx[];
|
||||
};
|
||||
#define INVALID_SMENDX -1
|
||||
#define cfg_smendx(cfg, fw, i) \
|
||||
(i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i])
|
||||
#define for_each_cfg_sme(cfg, fw, i, idx) \
|
||||
for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i)
|
||||
|
||||
static bool using_legacy_binding, using_generic_binding;
|
||||
|
||||
static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu)
|
||||
|
|
@ -234,19 +203,6 @@ static int arm_smmu_register_legacy_master(struct device *dev,
|
|||
}
|
||||
#endif /* CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS */
|
||||
|
||||
static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
|
||||
{
|
||||
int idx;
|
||||
|
||||
do {
|
||||
idx = find_next_zero_bit(map, end, start);
|
||||
if (idx == end)
|
||||
return -ENOSPC;
|
||||
} while (test_and_set_bit(idx, map));
|
||||
|
||||
return idx;
|
||||
}
|
||||
|
||||
static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
|
||||
{
|
||||
clear_bit(idx, map);
|
||||
|
|
@ -552,11 +508,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
|
|||
cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
|
||||
cb->ttbr[1] = 0;
|
||||
} else {
|
||||
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
|
||||
cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID,
|
||||
cfg->asid);
|
||||
cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
|
||||
cfg->asid);
|
||||
cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
|
||||
cfg->asid);
|
||||
|
||||
if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
|
||||
cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
|
||||
else
|
||||
cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
|
||||
}
|
||||
} else {
|
||||
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
|
||||
|
|
@ -574,7 +534,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
|
|||
}
|
||||
}
|
||||
|
||||
static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
|
||||
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
|
||||
{
|
||||
u32 reg;
|
||||
bool stage1;
|
||||
|
|
@ -660,8 +620,19 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
|
|||
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
|
||||
}
|
||||
|
||||
static int arm_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
|
||||
struct arm_smmu_device *smmu,
|
||||
struct device *dev, unsigned int start)
|
||||
{
|
||||
if (smmu->impl && smmu->impl->alloc_context_bank)
|
||||
return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start);
|
||||
|
||||
return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks);
|
||||
}
|
||||
|
||||
static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
||||
struct arm_smmu_device *smmu)
|
||||
struct arm_smmu_device *smmu,
|
||||
struct device *dev)
|
||||
{
|
||||
int irq, start, ret = 0;
|
||||
unsigned long ias, oas;
|
||||
|
|
@ -776,10 +747,13 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
|||
ret = -EINVAL;
|
||||
goto out_unlock;
|
||||
}
|
||||
ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
|
||||
smmu->num_context_banks);
|
||||
if (ret < 0)
|
||||
|
||||
ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start);
|
||||
if (ret < 0) {
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
smmu_domain->smmu = smmu;
|
||||
|
||||
cfg->cbndx = ret;
|
||||
if (smmu->version < ARM_SMMU_V2) {
|
||||
|
|
@ -794,13 +768,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
|||
else
|
||||
cfg->asid = cfg->cbndx;
|
||||
|
||||
smmu_domain->smmu = smmu;
|
||||
if (smmu->impl && smmu->impl->init_context) {
|
||||
ret = smmu->impl->init_context(smmu_domain);
|
||||
if (ret)
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
pgtbl_cfg = (struct io_pgtable_cfg) {
|
||||
.pgsize_bitmap = smmu->pgsize_bitmap,
|
||||
.ias = ias,
|
||||
|
|
@ -810,6 +777,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
|||
.iommu_dev = smmu->dev,
|
||||
};
|
||||
|
||||
if (smmu->impl && smmu->impl->init_context) {
|
||||
ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev);
|
||||
if (ret)
|
||||
goto out_clear_smmu;
|
||||
}
|
||||
|
||||
if (smmu_domain->non_strict)
|
||||
pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
|
||||
|
||||
|
|
@ -821,7 +794,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
|||
|
||||
/* Update the domain's page sizes to reflect the page table format */
|
||||
domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
|
||||
domain->geometry.aperture_end = (1UL << ias) - 1;
|
||||
|
||||
if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
|
||||
domain->geometry.aperture_start = ~0UL << ias;
|
||||
domain->geometry.aperture_end = ~0UL;
|
||||
} else {
|
||||
domain->geometry.aperture_end = (1UL << ias) - 1;
|
||||
}
|
||||
|
||||
domain->geometry.force_aperture = true;
|
||||
|
||||
/* Initialise the context bank with our page table cfg */
|
||||
|
|
@ -1182,7 +1162,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
|||
return ret;
|
||||
|
||||
/* Ensure that the domain is finalised */
|
||||
ret = arm_smmu_init_domain_context(domain, smmu);
|
||||
ret = arm_smmu_init_domain_context(domain, smmu, dev);
|
||||
if (ret < 0)
|
||||
goto rpm_put;
|
||||
|
||||
|
|
|
|||
|
|
@ -169,10 +169,12 @@ enum arm_smmu_cbar_type {
|
|||
#define ARM_SMMU_CB_TCR 0x30
|
||||
#define ARM_SMMU_TCR_EAE BIT(31)
|
||||
#define ARM_SMMU_TCR_EPD1 BIT(23)
|
||||
#define ARM_SMMU_TCR_A1 BIT(22)
|
||||
#define ARM_SMMU_TCR_TG0 GENMASK(15, 14)
|
||||
#define ARM_SMMU_TCR_SH0 GENMASK(13, 12)
|
||||
#define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10)
|
||||
#define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8)
|
||||
#define ARM_SMMU_TCR_EPD0 BIT(7)
|
||||
#define ARM_SMMU_TCR_T0SZ GENMASK(5, 0)
|
||||
|
||||
#define ARM_SMMU_VTCR_RES1 BIT(31)
|
||||
|
|
@ -254,6 +256,21 @@ enum arm_smmu_implementation {
|
|||
QCOM_SMMUV2,
|
||||
};
|
||||
|
||||
struct arm_smmu_s2cr {
|
||||
struct iommu_group *group;
|
||||
int count;
|
||||
enum arm_smmu_s2cr_type type;
|
||||
enum arm_smmu_s2cr_privcfg privcfg;
|
||||
u8 cbndx;
|
||||
};
|
||||
|
||||
struct arm_smmu_smr {
|
||||
u16 mask;
|
||||
u16 id;
|
||||
bool valid;
|
||||
bool pinned;
|
||||
};
|
||||
|
||||
struct arm_smmu_device {
|
||||
struct device *dev;
|
||||
|
||||
|
|
@ -329,6 +346,13 @@ struct arm_smmu_cfg {
|
|||
};
|
||||
#define ARM_SMMU_INVALID_IRPTNDX 0xff
|
||||
|
||||
struct arm_smmu_cb {
|
||||
u64 ttbr[2];
|
||||
u32 tcr[2];
|
||||
u32 mair[2];
|
||||
struct arm_smmu_cfg *cfg;
|
||||
};
|
||||
|
||||
enum arm_smmu_domain_stage {
|
||||
ARM_SMMU_DOMAIN_S1 = 0,
|
||||
ARM_SMMU_DOMAIN_S2,
|
||||
|
|
@ -348,23 +372,39 @@ struct arm_smmu_domain {
|
|||
struct iommu_domain domain;
|
||||
};
|
||||
|
||||
static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)
|
||||
struct arm_smmu_master_cfg {
|
||||
struct arm_smmu_device *smmu;
|
||||
s16 smendx[];
|
||||
};
|
||||
|
||||
static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg)
|
||||
{
|
||||
return ARM_SMMU_TCR_EPD1 |
|
||||
FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
|
||||
u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
|
||||
FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
|
||||
|
||||
/*
|
||||
* When TTBR1 is selected shift the TCR fields by 16 bits and disable
|
||||
* translation in TTBR0
|
||||
*/
|
||||
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
|
||||
tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
|
||||
tcr |= ARM_SMMU_TCR_EPD0;
|
||||
} else
|
||||
tcr |= ARM_SMMU_TCR_EPD1;
|
||||
|
||||
return tcr;
|
||||
}
|
||||
|
||||
static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg)
|
||||
static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg)
|
||||
{
|
||||
return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) |
|
||||
FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM);
|
||||
}
|
||||
|
||||
static inline u32 arm_smmu_lpae_vtcr(struct io_pgtable_cfg *cfg)
|
||||
static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg)
|
||||
{
|
||||
return ARM_SMMU_VTCR_RES1 |
|
||||
FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) |
|
||||
|
|
@ -386,14 +426,37 @@ struct arm_smmu_impl {
|
|||
u64 val);
|
||||
int (*cfg_probe)(struct arm_smmu_device *smmu);
|
||||
int (*reset)(struct arm_smmu_device *smmu);
|
||||
int (*init_context)(struct arm_smmu_domain *smmu_domain);
|
||||
int (*init_context)(struct arm_smmu_domain *smmu_domain,
|
||||
struct io_pgtable_cfg *cfg, struct device *dev);
|
||||
void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
|
||||
int status);
|
||||
int (*def_domain_type)(struct device *dev);
|
||||
irqreturn_t (*global_fault)(int irq, void *dev);
|
||||
irqreturn_t (*context_fault)(int irq, void *dev);
|
||||
int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain,
|
||||
struct arm_smmu_device *smmu,
|
||||
struct device *dev, int start);
|
||||
};
|
||||
|
||||
#define INVALID_SMENDX -1
|
||||
#define cfg_smendx(cfg, fw, i) \
|
||||
(i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i])
|
||||
#define for_each_cfg_sme(cfg, fw, i, idx) \
|
||||
for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i)
|
||||
|
||||
static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
|
||||
{
|
||||
int idx;
|
||||
|
||||
do {
|
||||
idx = find_next_zero_bit(map, end, start);
|
||||
if (idx == end)
|
||||
return -ENOSPC;
|
||||
} while (test_and_set_bit(idx, map));
|
||||
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
|
||||
{
|
||||
return smmu->base + (n << smmu->pgshift);
|
||||
|
|
@ -458,6 +521,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
|
|||
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
|
||||
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
|
||||
|
||||
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
|
||||
int arm_mmu500_reset(struct arm_smmu_device *smmu);
|
||||
|
||||
#endif /* _ARM_SMMU_H */
|
||||
|
|
|
|||
|
|
@ -584,8 +584,10 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
|||
* index into qcom_iommu->ctxs:
|
||||
*/
|
||||
if (WARN_ON(asid < 1) ||
|
||||
WARN_ON(asid > qcom_iommu->num_ctxs))
|
||||
WARN_ON(asid > qcom_iommu->num_ctxs)) {
|
||||
put_device(&iommu_pdev->dev);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!dev_iommu_priv_get(dev)) {
|
||||
dev_iommu_priv_set(dev, qcom_iommu);
|
||||
|
|
@ -594,8 +596,10 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
|||
* multiple different iommu devices. Multiple context
|
||||
* banks are ok, but multiple devices are not:
|
||||
*/
|
||||
if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev)))
|
||||
if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) {
|
||||
put_device(&iommu_pdev->dev);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return iommu_fwspec_add_ids(dev, &asid, 1);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
|
||||
#include <asm/barrier.h>
|
||||
|
||||
#include "io-pgtable-arm.h"
|
||||
|
||||
#define ARM_LPAE_MAX_ADDR_BITS 52
|
||||
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
|
||||
#define ARM_LPAE_MAX_LEVELS 4
|
||||
|
|
@ -100,23 +102,6 @@
|
|||
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
|
||||
|
||||
/* Register bits */
|
||||
#define ARM_LPAE_TCR_TG0_4K 0
|
||||
#define ARM_LPAE_TCR_TG0_64K 1
|
||||
#define ARM_LPAE_TCR_TG0_16K 2
|
||||
|
||||
#define ARM_LPAE_TCR_TG1_16K 1
|
||||
#define ARM_LPAE_TCR_TG1_4K 2
|
||||
#define ARM_LPAE_TCR_TG1_64K 3
|
||||
|
||||
#define ARM_LPAE_TCR_SH_NS 0
|
||||
#define ARM_LPAE_TCR_SH_OS 2
|
||||
#define ARM_LPAE_TCR_SH_IS 3
|
||||
|
||||
#define ARM_LPAE_TCR_RGN_NC 0
|
||||
#define ARM_LPAE_TCR_RGN_WBWA 1
|
||||
#define ARM_LPAE_TCR_RGN_WT 2
|
||||
#define ARM_LPAE_TCR_RGN_WB 3
|
||||
|
||||
#define ARM_LPAE_VTCR_SL0_MASK 0x3
|
||||
|
||||
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
|
||||
|
|
@ -124,14 +109,6 @@
|
|||
#define ARM_LPAE_VTCR_PS_SHIFT 16
|
||||
#define ARM_LPAE_VTCR_PS_MASK 0x7
|
||||
|
||||
#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
|
||||
#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
|
||||
#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
|
||||
#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
|
||||
#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
|
||||
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
|
||||
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
|
||||
|
||||
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
|
||||
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
|
||||
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
|
||||
|
|
|
|||
30
drivers/iommu/io-pgtable-arm.h
Normal file
30
drivers/iommu/io-pgtable-arm.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef IO_PGTABLE_ARM_H_
|
||||
#define IO_PGTABLE_ARM_H_
|
||||
|
||||
#define ARM_LPAE_TCR_TG0_4K 0
|
||||
#define ARM_LPAE_TCR_TG0_64K 1
|
||||
#define ARM_LPAE_TCR_TG0_16K 2
|
||||
|
||||
#define ARM_LPAE_TCR_TG1_16K 1
|
||||
#define ARM_LPAE_TCR_TG1_4K 2
|
||||
#define ARM_LPAE_TCR_TG1_64K 3
|
||||
|
||||
#define ARM_LPAE_TCR_SH_NS 0
|
||||
#define ARM_LPAE_TCR_SH_OS 2
|
||||
#define ARM_LPAE_TCR_SH_IS 3
|
||||
|
||||
#define ARM_LPAE_TCR_RGN_NC 0
|
||||
#define ARM_LPAE_TCR_RGN_WBWA 1
|
||||
#define ARM_LPAE_TCR_RGN_WT 2
|
||||
#define ARM_LPAE_TCR_RGN_WB 3
|
||||
|
||||
#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
|
||||
#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
|
||||
#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
|
||||
#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
|
||||
#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
|
||||
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
|
||||
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
|
||||
|
||||
#endif /* IO_PGTABLE_ARM_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue