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ASoC: Fixes for v5.18

Browse source 
A collection of fixes that came in since the merge window, plus one new
 device ID for an x86 laptop.  Nothing that really stands out with
 particularly big impact outside of the affected device.
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Merge tag 'asoc-fix-v5.18-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes for v5.18

A collection of fixes that came in since the merge window, plus one new
device ID for an x86 laptop.  Nothing that really stands out with
particularly big impact outside of the affected device.
This commit is contained in:
Takashi Iwai 2022-04-19 17:26:01 +02:00
commit 0aea30a07e
13267 changed files with 1046320 additions and 310959 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/acpi/acpi_bus.h
View file

@ -480,6 +480,8 @@ void acpi_initialize_hp_context(struct acpi_device *adev,
/* acpi_device.dev.bus == &acpi_bus_type */
extern struct bus_type acpi_bus_type;
int acpi_bus_for_each_dev(int (*fn)(struct device *, void *), void *data);
/*
* Events
* ------

4
include/acpi/actypes.h
View file

@ -507,8 +507,12 @@ typedef u64 acpi_integer;
/* Pointer/Integer type conversions */
#define ACPI_TO_POINTER(i) ACPI_CAST_PTR (void, (acpi_size) (i))
#ifndef ACPI_TO_INTEGER
#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p, (void *) 0)
#endif
#ifndef ACPI_OFFSET
#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF (&(((d *) 0)->f), (void *) 0)
#endif
#define ACPI_PTR_TO_PHYSADDR(i) ACPI_TO_INTEGER(i)
/* Optimizations for 4-character (32-bit) acpi_name manipulation */

4
include/acpi/apei.h
View file

@ -27,14 +27,16 @@ extern int hest_disable;
extern int erst_disable;
#ifdef CONFIG_ACPI_APEI_GHES
extern bool ghes_disable;
void __init acpi_ghes_init(void);
#else
#define ghes_disable 1
static inline void acpi_ghes_init(void) { }
#endif
#ifdef CONFIG_ACPI_APEI
void __init acpi_hest_init(void);
#else
static inline void acpi_hest_init(void) { return; }
static inline void acpi_hest_init(void) { }
#endif
int erst_write(const struct cper_record_header *record);

5
include/acpi/platform/aclinux.h
View file

@ -114,6 +114,11 @@
#define acpi_raw_spinlock raw_spinlock_t *
#define acpi_cpu_flags unsigned long
#define acpi_uintptr_t uintptr_t
#define ACPI_TO_INTEGER(p) ((uintptr_t)(p))
#define ACPI_OFFSET(d, f) offsetof(d, f)
/* Use native linux version of acpi_os_allocate_zeroed */
#define USE_NATIVE_ALLOCATE_ZEROED

48
include/asm-generic/access_ok.h Normal file
View file

@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_ACCESS_OK_H__
#define __ASM_GENERIC_ACCESS_OK_H__
/*
* Checking whether a pointer is valid for user space access.
* These definitions work on most architectures, but overrides can
* be used where necessary.
*/
/*
* architectures with compat tasks have a variable TASK_SIZE and should
* override this to a constant.
*/
#ifndef TASK_SIZE_MAX
#define TASK_SIZE_MAX TASK_SIZE
#endif
#ifndef __access_ok
/*
* 'size' is a compile-time constant for most callers, so optimize for
* this case to turn the check into a single comparison against a constant
* limit and catch all possible overflows.
* On architectures with separate user address space (m68k, s390, parisc,
* sparc64) or those without an MMU, this should always return true.
*
* This version was originally contributed by Jonas Bonn for the
* OpenRISC architecture, and was found to be the most efficient
* for constant 'size' and 'limit' values.
*/
static inline int __access_ok(const void __user *ptr, unsigned long size)
{
unsigned long limit = TASK_SIZE_MAX;
unsigned long addr = (unsigned long)ptr;
if (IS_ENABLED(CONFIG_ALTERNATE_USER_ADDRESS_SPACE) ||
!IS_ENABLED(CONFIG_MMU))
return true;
return (size <= limit) && (addr <= (limit - size));
}
#endif
#ifndef access_ok
#define access_ok(addr, size) likely(__access_ok(addr, size))
#endif
#endif

12
include/asm-generic/bitops/instrumented-atomic.h
View file

@ -23,7 +23,7 @@
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void set_bit(long nr, volatile unsigned long *addr)
static __always_inline void set_bit(long nr, volatile unsigned long *addr)
{
instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
arch_set_bit(nr, addr);
@ -36,7 +36,7 @@ static inline void set_bit(long nr, volatile unsigned long *addr)
*
* This is a relaxed atomic operation (no implied memory barriers).
*/
static inline void clear_bit(long nr, volatile unsigned long *addr)
static __always_inline void clear_bit(long nr, volatile unsigned long *addr)
{
instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
arch_clear_bit(nr, addr);
@ -52,7 +52,7 @@ static inline void clear_bit(long nr, volatile unsigned long *addr)
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void change_bit(long nr, volatile unsigned long *addr)
static __always_inline void change_bit(long nr, volatile unsigned long *addr)
{
instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
arch_change_bit(nr, addr);
@ -65,7 +65,7 @@ static inline void change_bit(long nr, volatile unsigned long *addr)
*
* This is an atomic fully-ordered operation (implied full memory barrier).
*/
static inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
{
kcsan_mb();
instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
@ -79,7 +79,7 @@ static inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
*
* This is an atomic fully-ordered operation (implied full memory barrier).
*/
static inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
{
kcsan_mb();
instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
@ -93,7 +93,7 @@ static inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
*
* This is an atomic fully-ordered operation (implied full memory barrier).
*/
static inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
{
kcsan_mb();
instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));

16
include/asm-generic/bitops/instrumented-non-atomic.h
View file

@ -22,7 +22,7 @@
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static inline void __set_bit(long nr, volatile unsigned long *addr)
static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___set_bit(nr, addr);
@ -37,7 +37,7 @@ static inline void __set_bit(long nr, volatile unsigned long *addr)
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static inline void __clear_bit(long nr, volatile unsigned long *addr)
static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___clear_bit(nr, addr);
@ -52,13 +52,13 @@ static inline void __clear_bit(long nr, volatile unsigned long *addr)
* region of memory concurrently, the effect may be that only one operation
* succeeds.
*/
static inline void __change_bit(long nr, volatile unsigned long *addr)
static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
{
instrument_write(addr + BIT_WORD(nr), sizeof(long));
arch___change_bit(nr, addr);
}
static inline void __instrument_read_write_bitop(long nr, volatile unsigned long *addr)
static __always_inline void __instrument_read_write_bitop(long nr, volatile unsigned long *addr)
{
if (IS_ENABLED(CONFIG_KCSAN_ASSUME_PLAIN_WRITES_ATOMIC)) {
/*
@ -90,7 +90,7 @@ static inline void __instrument_read_write_bitop(long nr, volatile unsigned long
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_set_bit(nr, addr);
@ -104,7 +104,7 @@ static inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_clear_bit(nr, addr);
@ -118,7 +118,7 @@ static inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
* This operation is non-atomic. If two instances of this operation race, one
* can appear to succeed but actually fail.
*/
static inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
{
__instrument_read_write_bitop(nr, addr);
return arch___test_and_change_bit(nr, addr);
@ -129,7 +129,7 @@ static inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
* @nr: bit number to test
* @addr: Address to start counting from
*/
static inline bool test_bit(long nr, const volatile unsigned long *addr)
static __always_inline bool test_bit(long nr, const volatile unsigned long *addr)
{
instrument_atomic_read(addr + BIT_WORD(nr), sizeof(long));
return arch_test_bit(nr, addr);

7
include/asm-generic/hyperv-tlfs.h
View file

@ -183,11 +183,18 @@ enum HV_GENERIC_SET_FORMAT {
#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)
#define HV_HYPERCALL_FAST_BIT BIT(16)
#define HV_HYPERCALL_VARHEAD_OFFSET 17
#define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17)
#define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27)
#define HV_HYPERCALL_REP_COMP_OFFSET 32
#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)
#define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44)
#define HV_HYPERCALL_REP_START_OFFSET 48
#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)
#define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60)
#define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \
HV_HYPERCALL_RSVD1_MASK | \
HV_HYPERCALL_RSVD2_MASK)
/* hypercall status code */
#define HV_STATUS_SUCCESS 0

15
include/asm-generic/sections.h
View file

@ -59,11 +59,24 @@ extern char __noinstr_text_start[], __noinstr_text_end[];
extern __visible const void __nosave_begin, __nosave_end;
/* Function descriptor handling (if any). Override in asm/sections.h */
#ifndef dereference_function_descriptor
#ifdef CONFIG_HAVE_FUNCTION_DESCRIPTORS
void *dereference_function_descriptor(void *ptr);
void *dereference_kernel_function_descriptor(void *ptr);
#else
#define dereference_function_descriptor(p) ((void *)(p))
#define dereference_kernel_function_descriptor(p) ((void *)(p))
/* An address is simply the address of the function. */
typedef struct {
unsigned long addr;
} func_desc_t;
#endif
static inline bool have_function_descriptors(void)
{
return IS_ENABLED(CONFIG_HAVE_FUNCTION_DESCRIPTORS);
}
/**
* memory_contains - checks if an object is contained within a memory region
* @begin: virtual address of the beginning of the memory region

2
include/asm-generic/syscall.h
View file

@ -44,7 +44,7 @@ int syscall_get_nr(struct task_struct *task, struct pt_regs *regs);
*
* It's only valid to call this when @task is stopped for system
* call exit tracing (due to %SYSCALL_WORK_SYSCALL_TRACE or
* %SYSCALL_WORK_SYSCALL_AUDIT), after tracehook_report_syscall_entry()
* %SYSCALL_WORK_SYSCALL_AUDIT), after ptrace_report_syscall_entry()
* returned nonzero to prevent the system call from taking place.
*
* This rolls back the register state in @regs so it's as if the

4
include/asm-generic/tlb.h
View file

@ -180,7 +180,7 @@ struct mmu_table_batch {
struct rcu_head rcu;
#endif
unsigned int nr;
void *tables[0];
void *tables[];
};
#define MAX_TABLE_BATCH \
@ -227,7 +227,7 @@ struct mmu_gather_batch {
struct mmu_gather_batch *next;
unsigned int nr;
unsigned int max;
struct page *pages[0];
struct page *pages[];
};
#define MAX_GATHER_BATCH \

46
include/asm-generic/uaccess.h
View file

@ -8,6 +8,7 @@
* address space, e.g. all NOMMU machines.
*/
#include <linux/string.h>
#include <asm-generic/access_ok.h>
#ifdef CONFIG_UACCESS_MEMCPY
#include <asm/unaligned.h>
@ -77,8 +78,6 @@ do { \
goto err_label; \
} while (0)
#define HAVE_GET_KERNEL_NOFAULT 1
static inline __must_check unsigned long
raw_copy_from_user(void *to, const void __user * from, unsigned long n)
{
@ -96,49 +95,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n)
#define INLINE_COPY_TO_USER
#endif /* CONFIG_UACCESS_MEMCPY */
#ifdef CONFIG_SET_FS
#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
#ifndef KERNEL_DS
#define KERNEL_DS MAKE_MM_SEG(~0UL)
#endif
#ifndef USER_DS
#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1)
#endif
#ifndef get_fs
#define get_fs() (current_thread_info()->addr_limit)
static inline void set_fs(mm_segment_t fs)
{
current_thread_info()->addr_limit = fs;
}
#endif
#ifndef uaccess_kernel
#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg)
#endif
#ifndef user_addr_max
#define user_addr_max() (uaccess_kernel() ? ~0UL : TASK_SIZE)
#endif
#endif /* CONFIG_SET_FS */
#define access_ok(addr, size) __access_ok((unsigned long)(addr),(size))
/*
* The architecture should really override this if possible, at least
* doing a check on the get_fs()
*/
#ifndef __access_ok
static inline int __access_ok(unsigned long addr, unsigned long size)
{
return 1;
}
#endif
/*
* These are the main single-value transfer routines. They automatically
* use the right size if we just have the right pointer type.

26
include/asm-generic/unaligned.h
View file

@ -126,4 +126,30 @@ static inline void put_unaligned_le24(const u32 val, void *p)
__put_unaligned_le24(val, p);
}
static inline void __put_unaligned_be48(const u64 val, __u8 *p)
{
*p++ = val >> 40;
*p++ = val >> 32;
*p++ = val >> 24;
*p++ = val >> 16;
*p++ = val >> 8;
*p++ = val;
}
static inline void put_unaligned_be48(const u64 val, void *p)
{
__put_unaligned_be48(val, p);
}
static inline u64 __get_unaligned_be48(const u8 *p)
{
return (u64)p[0] << 40 | (u64)p[1] << 32 | p[2] << 24 |
p[3] << 16 | p[4] << 8 | p[5];
}
static inline u64 get_unaligned_be48(const void *p)
{
return __get_unaligned_be48(p);
}
#endif /* __ASM_GENERIC_UNALIGNED_H */

15
include/asm-generic/vmlinux.lds.h
View file

@ -321,16 +321,6 @@
#define THERMAL_TABLE(name)
#endif
#ifdef CONFIG_DTPM
#define DTPM_TABLE() \
. = ALIGN(8); \
__dtpm_table = .; \
KEEP(*(__dtpm_table)) \
__dtpm_table_end = .;
#else
#define DTPM_TABLE()
#endif
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
__dtb_start = .; \
@ -404,6 +394,7 @@
KEEP(*(__jump_table)) \
__stop___jump_table = .;
#ifdef CONFIG_HAVE_STATIC_CALL_INLINE
#define STATIC_CALL_DATA \
. = ALIGN(8); \
__start_static_call_sites = .; \
@ -412,6 +403,9 @@
__start_static_call_tramp_key = .; \
KEEP(*(.static_call_tramp_key)) \
__stop_static_call_tramp_key = .;
#else
#define STATIC_CALL_DATA
#endif
/*
* Allow architectures to handle ro_after_init data on their
@ -723,7 +717,6 @@
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(timer) \
THERMAL_TABLE(governor) \
DTPM_TABLE() \
EARLYCON_TABLE() \
LSM_TABLE() \
EARLY_LSM_TABLE() \

84
include/asm-generic/xor.h
View file

@ -8,7 +8,8 @@
#include <linux/prefetch.h>
static void
xor_8regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
xor_8regs_2(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2)
{
long lines = bytes / (sizeof (long)) / 8;
@ -27,8 +28,9 @@ xor_8regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
}
static void
xor_8regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3)
xor_8regs_3(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3)
{
long lines = bytes / (sizeof (long)) / 8;
@ -48,8 +50,10 @@ xor_8regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_8regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4)
xor_8regs_4(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4)
{
long lines = bytes / (sizeof (long)) / 8;
@ -70,8 +74,11 @@ xor_8regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_8regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4, unsigned long *p5)
xor_8regs_5(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4,
const unsigned long * __restrict p5)
{
long lines = bytes / (sizeof (long)) / 8;
@ -93,7 +100,8 @@ xor_8regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
xor_32regs_2(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2)
{
long lines = bytes / (sizeof (long)) / 8;
@ -129,8 +137,9 @@ xor_32regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
}
static void
xor_32regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3)
xor_32regs_3(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3)
{
long lines = bytes / (sizeof (long)) / 8;
@ -175,8 +184,10 @@ xor_32regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4)
xor_32regs_4(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4)
{
long lines = bytes / (sizeof (long)) / 8;
@ -230,8 +241,11 @@ xor_32regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4, unsigned long *p5)
xor_32regs_5(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4,
const unsigned long * __restrict p5)
{
long lines = bytes / (sizeof (long)) / 8;
@ -294,7 +308,8 @@ xor_32regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_8regs_p_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
xor_8regs_p_2(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
prefetchw(p1);
@ -320,8 +335,9 @@ xor_8regs_p_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
}
static void
xor_8regs_p_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3)
xor_8regs_p_3(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
prefetchw(p1);
@ -350,8 +366,10 @@ xor_8regs_p_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_8regs_p_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4)
xor_8regs_p_4(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
@ -384,8 +402,11 @@ xor_8regs_p_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_8regs_p_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4, unsigned long *p5)
xor_8regs_p_5(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4,
const unsigned long * __restrict p5)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
@ -421,7 +442,8 @@ xor_8regs_p_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_p_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
xor_32regs_p_2(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
@ -466,8 +488,9 @@ xor_32regs_p_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
}
static void
xor_32regs_p_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3)
xor_32regs_p_3(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
@ -523,8 +546,10 @@ xor_32regs_p_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_p_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4)
xor_32regs_p_4(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4)
{
long lines = bytes / (sizeof (long)) / 8 - 1;
@ -591,8 +616,11 @@ xor_32regs_p_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
}
static void
xor_32regs_p_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
unsigned long *p3, unsigned long *p4, unsigned long *p5)
xor_32regs_p_5(unsigned long bytes, unsigned long * __restrict p1,
const unsigned long * __restrict p2,
const unsigned long * __restrict p3,
const unsigned long * __restrict p4,
const unsigned long * __restrict p5)
{
long lines = bytes / (sizeof (long)) / 8 - 1;

1
include/clocksource/arm_arch_timer.h
View file

@ -56,6 +56,7 @@ enum arch_timer_spi_nr {
#define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
#define ARCH_TIMER_EVT_INTERVAL_SCALE (1 << 17) /* EVNTIS in the ARMv8 ARM */
#define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
#define ARCH_TIMER_EVT_STREAM_FREQ \

10
include/crypto/algapi.h
View file

@ -13,6 +13,8 @@
#include <linux/list.h>
#include <linux/types.h>
#include <asm/unaligned.h>
/*
* Maximum values for blocksize and alignmask, used to allocate
* static buffers that are big enough for any combination of
@ -154,9 +156,11 @@ static inline void crypto_xor(u8 *dst, const u8 *src, unsigned int size)
(size % sizeof(unsigned long)) == 0) {
unsigned long *d = (unsigned long *)dst;
unsigned long *s = (unsigned long *)src;
unsigned long l;
while (size > 0) {
*d++ ^= *s++;
l = get_unaligned(d) ^ get_unaligned(s++);
put_unaligned(l, d++);
size -= sizeof(unsigned long);
}
} else {
@ -173,9 +177,11 @@ static inline void crypto_xor_cpy(u8 *dst, const u8 *src1, const u8 *src2,
unsigned long *d = (unsigned long *)dst;
unsigned long *s1 = (unsigned long *)src1;
unsigned long *s2 = (unsigned long *)src2;
unsigned long l;
while (size > 0) {
*d++ = *s1++ ^ *s2++;
l = get_unaligned(s1++) ^ get_unaligned(s2++);
put_unaligned(l, d++);
size -= sizeof(unsigned long);
}
} else {

19
include/crypto/asym_tpm_subtype.h
View file

@ -1,19 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#ifndef _LINUX_ASYM_TPM_SUBTYPE_H
#define _LINUX_ASYM_TPM_SUBTYPE_H
#include <linux/keyctl.h>
struct tpm_key {
void *blob;
u32 blob_len;
uint16_t key_len; /* Size in bits of the key */
const void *pub_key; /* pointer inside blob to the public key bytes */
uint16_t pub_key_len; /* length of the public key */
};
struct tpm_key *tpm_key_create(const void *blob, uint32_t blob_len);
extern struct asymmetric_key_subtype asym_tpm_subtype;
#endif /* _LINUX_ASYM_TPM_SUBTYPE_H */

26
include/crypto/dh.h
View file

@ -24,21 +24,17 @@
*
* @key: Private DH key
* @p: Diffie-Hellman parameter P
* @q: Diffie-Hellman parameter Q
* @g: Diffie-Hellman generator G
* @key_size: Size of the private DH key
* @p_size: Size of DH parameter P
* @q_size: Size of DH parameter Q
* @g_size: Size of DH generator G
*/
struct dh {
void *key;
void *p;
void *q;
void *g;
const void *key;
const void *p;
const void *g;
unsigned int key_size;
unsigned int p_size;
unsigned int q_size;
unsigned int g_size;
};
@ -83,4 +79,20 @@ int crypto_dh_encode_key(char *buf, unsigned int len, const struct dh *params);
*/
int crypto_dh_decode_key(const char *buf, unsigned int len, struct dh *params);
/**
* __crypto_dh_decode_key() - decode a private key without parameter checks
* @buf: Buffer holding a packet key that should be decoded
* @len: Length of the packet private key buffer
* @params: Buffer allocated by the caller that is filled with the
* unpacked DH private key.
*
* Internal function providing the same services as the exported
* crypto_dh_decode_key(), but without any of those basic parameter
* checks conducted by the latter.
*
* Return: -EINVAL if buffer has insufficient size, 0 on success
*/
int __crypto_dh_decode_key(const char *buf, unsigned int len,
struct dh *params);
#endif

40
include/crypto/internal/blake2s.h
View file

@ -24,14 +24,11 @@ static inline void blake2s_set_lastblock(struct blake2s_state *state)
state->f[0] = -1;
}
typedef void (*blake2s_compress_t)(struct blake2s_state *state,
const u8 *block, size_t nblocks, u32 inc);
/* Helper functions for BLAKE2s shared by the library and shash APIs */
static inline void __blake2s_update(struct blake2s_state *state,
const u8 *in, size_t inlen,
blake2s_compress_t compress)
static __always_inline void
__blake2s_update(struct blake2s_state *state, const u8 *in, size_t inlen,
bool force_generic)
{
const size_t fill = BLAKE2S_BLOCK_SIZE - state->buflen;
@ -39,7 +36,12 @@ static inline void __blake2s_update(struct blake2s_state *state,
return;
if (inlen > fill) {
memcpy(state->buf + state->buflen, in, fill);
(*compress)(state, state->buf, 1, BLAKE2S_BLOCK_SIZE);
if (force_generic)
blake2s_compress_generic(state, state->buf, 1,
BLAKE2S_BLOCK_SIZE);
else
blake2s_compress(state, state->buf, 1,
BLAKE2S_BLOCK_SIZE);
state->buflen = 0;
in += fill;
inlen -= fill;
@ -47,7 +49,12 @@ static inline void __blake2s_update(struct blake2s_state *state,
if (inlen > BLAKE2S_BLOCK_SIZE) {
const size_t nblocks = DIV_ROUND_UP(inlen, BLAKE2S_BLOCK_SIZE);
/* Hash one less (full) block than strictly possible */
(*compress)(state, in, nblocks - 1, BLAKE2S_BLOCK_SIZE);
if (force_generic)
blake2s_compress_generic(state, in, nblocks - 1,
BLAKE2S_BLOCK_SIZE);
else
blake2s_compress(state, in, nblocks - 1,
BLAKE2S_BLOCK_SIZE);
in += BLAKE2S_BLOCK_SIZE * (nblocks - 1);
inlen -= BLAKE2S_BLOCK_SIZE * (nblocks - 1);
}
@ -55,13 +62,16 @@ static inline void __blake2s_update(struct blake2s_state *state,
state->buflen += inlen;
}
static inline void __blake2s_final(struct blake2s_state *state, u8 *out,
blake2s_compress_t compress)
static __always_inline void
__blake2s_final(struct blake2s_state *state, u8 *out, bool force_generic)
{
blake2s_set_lastblock(state);
memset(state->buf + state->buflen, 0,
BLAKE2S_BLOCK_SIZE - state->buflen); /* Padding */
(*compress)(state, state->buf, 1, state->buflen);
if (force_generic)
blake2s_compress_generic(state, state->buf, 1, state->buflen);
else
blake2s_compress(state, state->buf, 1, state->buflen);
cpu_to_le32_array(state->h, ARRAY_SIZE(state->h));
memcpy(out, state->h, state->outlen);
}
@ -99,20 +109,20 @@ static inline int crypto_blake2s_init(struct shash_desc *desc)
static inline int crypto_blake2s_update(struct shash_desc *desc,
const u8 *in, unsigned int inlen,
blake2s_compress_t compress)
bool force_generic)
{
struct blake2s_state *state = shash_desc_ctx(desc);
__blake2s_update(state, in, inlen, compress);
__blake2s_update(state, in, inlen, force_generic);
return 0;
}
static inline int crypto_blake2s_final(struct shash_desc *desc, u8 *out,
blake2s_compress_t compress)
bool force_generic)
{
struct blake2s_state *state = shash_desc_ctx(desc);
__blake2s_final(state, out, compress);
__blake2s_final(state, out, force_generic);
return 0;
}

158
include/crypto/internal/kpp.h
View file

@ -10,6 +10,38 @@
#include <crypto/kpp.h>
#include <crypto/algapi.h>
/**
* struct kpp_instance - KPP template instance
* @free: Callback getting invoked upon instance destruction. Must be set.
* @s: Internal. Generic crypto core instance state properly layout
* to alias with @alg as needed.
* @alg: The &struct kpp_alg implementation provided by the instance.
*/
struct kpp_instance {
void (*free)(struct kpp_instance *inst);
union {
struct {
char head[offsetof(struct kpp_alg, base)];
struct crypto_instance base;
} s;
struct kpp_alg alg;
};
};
/**
* struct crypto_kpp_spawn - KPP algorithm spawn
* @base: Internal. Generic crypto core spawn state.
*
* Template instances can get a hold on some inner KPP algorithm by
* binding a &struct crypto_kpp_spawn via
* crypto_grab_kpp(). Transforms may subsequently get instantiated
* from the referenced inner &struct kpp_alg by means of
* crypto_spawn_kpp().
*/
struct crypto_kpp_spawn {
struct crypto_spawn base;
};
/*
* Transform internal helpers.
*/
@ -33,6 +65,62 @@ static inline const char *kpp_alg_name(struct crypto_kpp *tfm)
return crypto_kpp_tfm(tfm)->__crt_alg->cra_name;
}
/*
* Template instance internal helpers.
*/
/**
* kpp_crypto_instance() - Cast a &struct kpp_instance to the corresponding
* generic &struct crypto_instance.
* @inst: Pointer to the &struct kpp_instance to be cast.
* Return: A pointer to the &struct crypto_instance embedded in @inst.
*/
static inline struct crypto_instance *kpp_crypto_instance(
struct kpp_instance *inst)
{
return &inst->s.base;
}
/**
* kpp_instance() - Cast a generic &struct crypto_instance to the corresponding
* &struct kpp_instance.
* @inst: Pointer to the &struct crypto_instance to be cast.
* Return: A pointer to the &struct kpp_instance @inst is embedded in.
*/
static inline struct kpp_instance *kpp_instance(struct crypto_instance *inst)
{
return container_of(inst, struct kpp_instance, s.base);
}
/**
* kpp_alg_instance() - Get the &struct kpp_instance a given KPP transform has
* been instantiated from.
* @kpp: The KPP transform instantiated from some &struct kpp_instance.
* Return: The &struct kpp_instance associated with @kpp.
*/
static inline struct kpp_instance *kpp_alg_instance(struct crypto_kpp *kpp)
{
return kpp_instance(crypto_tfm_alg_instance(&kpp->base));
}
/**
* kpp_instance_ctx() - Get a pointer to a &struct kpp_instance's implementation
* specific context data.
* @inst: The &struct kpp_instance whose context data to access.
*
* A KPP template implementation may allocate extra memory beyond the
* end of a &struct kpp_instance instantiated from &crypto_template.create().
* This function provides a means to obtain a pointer to this area.
*
* Return: A pointer to the implementation specific context data.
*/
static inline void *kpp_instance_ctx(struct kpp_instance *inst)
{
return crypto_instance_ctx(kpp_crypto_instance(inst));
}
/*
* KPP algorithm (un)registration functions.
*/
/**
* crypto_register_kpp() -- Register key-agreement protocol primitives algorithm
*
@ -56,4 +144,74 @@ int crypto_register_kpp(struct kpp_alg *alg);
*/
void crypto_unregister_kpp(struct kpp_alg *alg);
/**
* kpp_register_instance() - Register a KPP template instance.
* @tmpl: The instantiating template.
* @inst: The KPP template instance to be registered.
* Return: %0 on success, negative error code otherwise.
*/
int kpp_register_instance(struct crypto_template *tmpl,
struct kpp_instance *inst);
/*
* KPP spawn related functions.
*/
/**
* crypto_grab_kpp() - Look up a KPP algorithm and bind a spawn to it.
* @spawn: The KPP spawn to bind.
* @inst: The template instance owning @spawn.
* @name: The KPP algorithm name to look up.
* @type: The type bitset to pass on to the lookup.
* @mask: The mask bismask to pass on to the lookup.
* Return: %0 on success, a negative error code otherwise.
*/
int crypto_grab_kpp(struct crypto_kpp_spawn *spawn,
struct crypto_instance *inst,
const char *name, u32 type, u32 mask);
/**
* crypto_drop_kpp() - Release a spawn previously bound via crypto_grab_kpp().
* @spawn: The spawn to release.
*/
static inline void crypto_drop_kpp(struct crypto_kpp_spawn *spawn)
{
crypto_drop_spawn(&spawn->base);
}
/**
* crypto_spawn_kpp_alg() - Get the algorithm a KPP spawn has been bound to.
* @spawn: The spawn to get the referenced &struct kpp_alg for.
*
* This function as well as the returned result are safe to use only
* after @spawn has been successfully bound via crypto_grab_kpp() and
* up to until the template instance owning @spawn has either been
* registered successfully or the spawn has been released again via
* crypto_drop_spawn().
*
* Return: A pointer to the &struct kpp_alg referenced from the spawn.
*/
static inline struct kpp_alg *crypto_spawn_kpp_alg(
struct crypto_kpp_spawn *spawn)
{
return container_of(spawn->base.alg, struct kpp_alg, base);
}
/**
* crypto_spawn_kpp() - Create a transform from a KPP spawn.
* @spawn: The spawn previously bound to some &struct kpp_alg via
* crypto_grab_kpp().
*
* Once a &struct crypto_kpp_spawn has been successfully bound to a
* &struct kpp_alg via crypto_grab_kpp(), transforms for the latter
* may get instantiated from the former by means of this function.
*
* Return: A pointer to the freshly created KPP transform on success
* or an ``ERR_PTR()`` otherwise.
*/
static inline struct crypto_kpp *crypto_spawn_kpp(
struct crypto_kpp_spawn *spawn)
{
return crypto_spawn_tfm2(&spawn->base);
}
#endif

34
include/crypto/sm3.h
View file

@ -1,5 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Common values for SM3 algorithm
*
* Copyright (C) 2017 ARM Limited or its affiliates.
* Copyright (C) 2017 Gilad Ben-Yossef <gilad@benyossef.com>
* Copyright (C) 2021 Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
*/
#ifndef _CRYPTO_SM3_H
@ -30,13 +35,30 @@ struct sm3_state {
u8 buffer[SM3_BLOCK_SIZE];
};
struct shash_desc;
/*
* Stand-alone implementation of the SM3 algorithm. It is designed to
* have as little dependencies as possible so it can be used in the
* kexec_file purgatory. In other cases you should generally use the
* hash APIs from include/crypto/hash.h. Especially when hashing large
* amounts of data as those APIs may be hw-accelerated.
*
* For details see lib/crypto/sm3.c
*/
extern int crypto_sm3_update(struct shash_desc *desc, const u8 *data,
unsigned int len);
static inline void sm3_init(struct sm3_state *sctx)
{
sctx->state[0] = SM3_IVA;
sctx->state[1] = SM3_IVB;
sctx->state[2] = SM3_IVC;
sctx->state[3] = SM3_IVD;
sctx->state[4] = SM3_IVE;
sctx->state[5] = SM3_IVF;
sctx->state[6] = SM3_IVG;
sctx->state[7] = SM3_IVH;
sctx->count = 0;
}
extern int crypto_sm3_final(struct shash_desc *desc, u8 *out);
void sm3_update(struct sm3_state *sctx, const u8 *data, unsigned int len);
void sm3_final(struct sm3_state *sctx, u8 *out);
extern int crypto_sm3_finup(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *hash);
#endif

4
include/drm/bridge/dw_mipi_dsi.h
View file

@ -51,7 +51,9 @@ struct dw_mipi_dsi_plat_data {
unsigned int max_data_lanes;
enum drm_mode_status (*mode_valid)(void *priv_data,
const struct drm_display_mode *mode);
const struct drm_display_mode *mode,
unsigned long mode_flags,
u32 lanes, u32 format);
const struct dw_mipi_dsi_phy_ops *phy_ops;
const struct dw_mipi_dsi_host_ops *host_ops;

0
include/drm/drm_dp_aux_bus.h → include/drm/dp/drm_dp_aux_bus.h
View file

0
include/drm/drm_dp_dual_mode_helper.h → include/drm/dp/drm_dp_dual_mode_helper.h
View file

35
include/drm/drm_dp_helper.h → include/drm/dp/drm_dp_helper.h
View file

@ -456,7 +456,7 @@ struct drm_panel;
#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
#define DP_PCON_DSC_ENCODER 0x092
# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
@ -560,6 +560,7 @@ struct drm_panel;
# define DP_TRAINING_PATTERN_DISABLE 0
# define DP_TRAINING_PATTERN_1 1
# define DP_TRAINING_PATTERN_2 2
# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
# define DP_TRAINING_PATTERN_MASK 0x3
@ -738,11 +739,13 @@ struct drm_panel;
DP_LANE_CHANNEL_EQ_DONE | \
DP_LANE_SYMBOL_LOCKED)
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0)
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
#define DP_LINK_STATUS_UPDATED (1 << 7)
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0)
#define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
#define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
#define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
#define DP_LINK_STATUS_UPDATED (1 << 7)
#define DP_SINK_STATUS 0x205
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
@ -1038,11 +1041,8 @@ struct drm_panel;
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
/* DPRX Event Status Indicator */
#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
/* 0-5 sink count */
# define DP_SINK_COUNT_CP_READY (1 << 6)
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
@ -1115,6 +1115,7 @@ struct drm_panel;
# define DP_UHBR13_5 (1 << 2)
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
@ -1350,6 +1351,7 @@ struct drm_panel;
# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
enum drm_dp_phy {
DP_PHY_DPRX,
@ -1528,8 +1530,6 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
int lane);
u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
unsigned int lane);
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
@ -1552,6 +1552,15 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
u8 drm_dp_link_rate_to_bw_code(int link_rate);
int drm_dp_bw_code_to_link_rate(u8 link_bw);

2
include/drm/drm_dp_mst_helper.h → include/drm/dp/drm_dp_mst_helper.h
View file

@ -23,7 +23,7 @@
#define _DRM_DP_MST_HELPER_H_
#include <linux/types.h>
#include <drm/drm_dp_helper.h>
#include <drm/dp/drm_dp_helper.h>
#include <drm/drm_atomic.h>
#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS)

7
include/drm/drm_bridge.h
View file

@ -649,6 +649,13 @@ struct drm_bridge_funcs {
* the DRM_BRIDGE_OP_HPD flag in their &drm_bridge->ops.
*/
void (*hpd_disable)(struct drm_bridge *bridge);
/**
* @debugfs_init:
*
* Allows bridges to create bridge-specific debugfs files.
*/
void (*debugfs_init)(struct drm_bridge *bridge, struct dentry *root);
};
/**

159
include/drm/drm_buddy.h Normal file
View file

@ -0,0 +1,159 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2021 Intel Corporation
*/
#ifndef __DRM_BUDDY_H__
#define __DRM_BUDDY_H__
#include <linux/bitops.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <drm/drm_print.h>
#define range_overflows(start, size, max) ({ \
typeof(start) start__ = (start); \
typeof(size) size__ = (size); \
typeof(max) max__ = (max); \
(void)(&start__ == &size__); \
(void)(&start__ == &max__); \
start__ >= max__ || size__ > max__ - start__; \
})
#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0)
#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1)
struct drm_buddy_block {
#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
#define DRM_BUDDY_ALLOCATED (1 << 10)
#define DRM_BUDDY_FREE (2 << 10)
#define DRM_BUDDY_SPLIT (3 << 10)
/* Free to be used, if needed in the future */
#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6)
#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0)
u64 header;
struct drm_buddy_block *left;
struct drm_buddy_block *right;
struct drm_buddy_block *parent;
void *private; /* owned by creator */
/*
* While the block is allocated by the user through drm_buddy_alloc*,
* the user has ownership of the link, for example to maintain within
* a list, if so desired. As soon as the block is freed with
* drm_buddy_free* ownership is given back to the mm.
*/
struct list_head link;
struct list_head tmp_link;
};
/* Order-zero must be at least PAGE_SIZE */
#define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT)
/*
* Binary Buddy System.
*
* Locking should be handled by the user, a simple mutex around
* drm_buddy_alloc* and drm_buddy_free* should suffice.
*/
struct drm_buddy {
/* Maintain a free list for each order. */
struct list_head *free_list;
/*
* Maintain explicit binary tree(s) to track the allocation of the
* address space. This gives us a simple way of finding a buddy block
* and performing the potentially recursive merge step when freeing a
* block. Nodes are either allocated or free, in which case they will
* also exist on the respective free list.
*/
struct drm_buddy_block **roots;
/*
* Anything from here is public, and remains static for the lifetime of
* the mm. Everything above is considered do-not-touch.
*/
unsigned int n_roots;
unsigned int max_order;
/* Must be at least PAGE_SIZE */
u64 chunk_size;
u64 size;
u64 avail;
};
static inline u64
drm_buddy_block_offset(struct drm_buddy_block *block)
{
return block->header & DRM_BUDDY_HEADER_OFFSET;
}
static inline unsigned int
drm_buddy_block_order(struct drm_buddy_block *block)
{
return block->header & DRM_BUDDY_HEADER_ORDER;
}
static inline unsigned int
drm_buddy_block_state(struct drm_buddy_block *block)
{
return block->header & DRM_BUDDY_HEADER_STATE;
}
static inline bool
drm_buddy_block_is_allocated(struct drm_buddy_block *block)
{
return drm_buddy_block_state(block) == DRM_BUDDY_ALLOCATED;
}
static inline bool
drm_buddy_block_is_free(struct drm_buddy_block *block)
{
return drm_buddy_block_state(block) == DRM_BUDDY_FREE;
}
static inline bool
drm_buddy_block_is_split(struct drm_buddy_block *block)
{
return drm_buddy_block_state(block) == DRM_BUDDY_SPLIT;
}
static inline u64
drm_buddy_block_size(struct drm_buddy *mm,
struct drm_buddy_block *block)
{
return mm->chunk_size << drm_buddy_block_order(block);
}
int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size);
void drm_buddy_fini(struct drm_buddy *mm);
struct drm_buddy_block *
drm_get_buddy(struct drm_buddy_block *block);
int drm_buddy_alloc_blocks(struct drm_buddy *mm,
u64 start, u64 end, u64 size,
u64 min_page_size,
struct list_head *blocks,
unsigned long flags);
int drm_buddy_block_trim(struct drm_buddy *mm,
u64 new_size,
struct list_head *blocks);
void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block);
void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects);
void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p);
void drm_buddy_block_print(struct drm_buddy *mm,
struct drm_buddy_block *block,
struct drm_printer *p);
#endif

6
include/drm/drm_cache.h
View file

@ -35,7 +35,7 @@
#include <linux/scatterlist.h>
struct dma_buf_map;
struct iosys_map;
void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
void drm_clflush_sg(struct sg_table *st);
@ -74,7 +74,7 @@ static inline bool drm_arch_can_wc_memory(void)
void drm_memcpy_init_early(void);
void drm_memcpy_from_wc(struct dma_buf_map *dst,
const struct dma_buf_map *src,
void drm_memcpy_from_wc(struct iosys_map *dst,
const struct iosys_map *src,
unsigned long len);
#endif

7
include/drm/drm_client.h
View file

@ -3,7 +3,7 @@
#ifndef _DRM_CLIENT_H_
#define _DRM_CLIENT_H_
#include <linux/dma-buf-map.h>
#include <linux/iosys-map.h>
#include <linux/lockdep.h>
#include <linux/mutex.h>
#include <linux/types.h>
@ -144,7 +144,7 @@ struct drm_client_buffer {
/**
* @map: Virtual address for the buffer
*/
struct dma_buf_map map;
struct iosys_map map;
/**
* @fb: DRM framebuffer
@ -156,7 +156,8 @@ struct drm_client_buffer *
drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);
void drm_client_framebuffer_delete(struct drm_client_buffer *buffer);
int drm_client_framebuffer_flush(struct drm_client_buffer *buffer, struct drm_rect *rect);
int drm_client_buffer_vmap(struct drm_client_buffer *buffer, struct dma_buf_map *map);
int drm_client_buffer_vmap(struct drm_client_buffer *buffer,
struct iosys_map *map);
void drm_client_buffer_vunmap(struct drm_client_buffer *buffer);
int drm_client_modeset_create(struct drm_client_dev *client);

25
include/drm/drm_connector.h
View file

@ -522,9 +522,9 @@ struct drm_display_info {
enum subpixel_order subpixel_order;
#define DRM_COLOR_FORMAT_RGB444 (1<<0)
#define DRM_COLOR_FORMAT_YCRCB444 (1<<1)
#define DRM_COLOR_FORMAT_YCRCB422 (1<<2)
#define DRM_COLOR_FORMAT_YCRCB420 (1<<3)
#define DRM_COLOR_FORMAT_YCBCR444 (1<<1)
#define DRM_COLOR_FORMAT_YCBCR422 (1<<2)
#define DRM_COLOR_FORMAT_YCBCR420 (1<<3)
/**
* @panel_orientation: Read only connector property for built-in panels,
@ -592,10 +592,16 @@ struct drm_display_info {
bool rgb_quant_range_selectable;
/**
* @edid_hdmi_dc_modes: Mask of supported hdmi deep color modes. Even
* more stuff redundant with @bus_formats.
* @edid_hdmi_rgb444_dc_modes: Mask of supported hdmi deep color modes
* in RGB 4:4:4. Even more stuff redundant with @bus_formats.
*/
u8 edid_hdmi_dc_modes;
u8 edid_hdmi_rgb444_dc_modes;
/**
* @edid_hdmi_ycbcr444_dc_modes: Mask of supported hdmi deep color
* modes in YCbCr 4:4:4. Even more stuff redundant with @bus_formats.
*/
u8 edid_hdmi_ycbcr444_dc_modes;
/**
* @cea_rev: CEA revision of the HDMI sink.
@ -1136,6 +1142,13 @@ struct drm_connector_funcs {
* has been received from a source outside the display driver / device.
*/
void (*oob_hotplug_event)(struct drm_connector *connector);
/**
* @debugfs_init:
*
* Allows connectors to create connector-specific debugfs files.
*/
void (*debugfs_init)(struct drm_connector *connector, struct dentry *root);
};
/**

12
include/drm/drm_crtc.h
View file

@ -285,6 +285,10 @@ struct drm_crtc_state {
* Lookup table for converting pixel data after the color conversion
* matrix @ctm. See drm_crtc_enable_color_mgmt(). The blob (if not
* NULL) is an array of &struct drm_color_lut.
*
* Note that for mostly historical reasons stemming from Xorg heritage,
* this is also used to store the color map (also sometimes color lut,
* CLUT or color palette) for indexed formats like DRM_FORMAT_C8.
*/
struct drm_property_blob *gamma_lut;
@ -1075,12 +1079,18 @@ struct drm_crtc {
/**
* @gamma_size: Size of legacy gamma ramp reported to userspace. Set up
* by calling drm_mode_crtc_set_gamma_size().
*
* Note that atomic drivers need to instead use
* &drm_crtc_state.gamma_lut. See drm_crtc_enable_color_mgmt().
*/
uint32_t gamma_size;
/**
* @gamma_store: Gamma ramp values used by the legacy SETGAMMA and
* GETGAMMA IOCTls. Set up by calling drm_mode_crtc_set_gamma_size().
*
* Note that atomic drivers need to instead use
* &drm_crtc_state.gamma_lut. See drm_crtc_enable_color_mgmt().
*/
uint16_t *gamma_store;
@ -1135,14 +1145,12 @@ struct drm_crtc {
*/
spinlock_t commit_lock;
#ifdef CONFIG_DEBUG_FS
/**
* @debugfs_entry:
*
* Debugfs directory for this CRTC.
*/
struct dentry *debugfs_entry;
#endif
/**
* @crc:

2
include/drm/drm_dsc.h
View file

@ -8,7 +8,7 @@
#ifndef DRM_DSC_H_
#define DRM_DSC_H_
#include <drm/drm_dp_helper.h>
#include <drm/dp/drm_dp_helper.h>
/* VESA Display Stream Compression DSC 1.2 constants */
#define DSC_NUM_BUF_RANGES 15

4
include/drm/drm_edid.h
View file

@ -401,8 +401,8 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
const struct drm_display_mode *mode);
void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,

4
include/drm/drm_format_helper.h
View file

@ -43,4 +43,8 @@ int drm_fb_blit_toio(void __iomem *dst, unsigned int dst_pitch, uint32_t dst_for
const void *vmap, const struct drm_framebuffer *fb,
const struct drm_rect *rect);
void drm_fb_xrgb8888_to_mono_reversed(void *dst, unsigned int dst_pitch, const void *src,
const struct drm_framebuffer *fb,
const struct drm_rect *clip);
#endif /* __LINUX_DRM_FORMAT_HELPER_H */

6
include/drm/drm_gem.h
View file

@ -39,7 +39,7 @@
#include <drm/drm_vma_manager.h>
struct dma_buf_map;
struct iosys_map;
struct drm_gem_object;
/**
@ -139,7 +139,7 @@ struct drm_gem_object_funcs {
*
* This callback is optional.
*/
int (*vmap)(struct drm_gem_object *obj, struct dma_buf_map *map);
int (*vmap)(struct drm_gem_object *obj, struct iosys_map *map);
/**
* @vunmap:
@ -149,7 +149,7 @@ struct drm_gem_object_funcs {
*
* This callback is optional.
*/
void (*vunmap)(struct drm_gem_object *obj, struct dma_buf_map *map);
void (*vunmap)(struct drm_gem_object *obj, struct iosys_map *map);
/**
* @mmap:

6
include/drm/drm_gem_atomic_helper.h
View file

@ -3,7 +3,7 @@
#ifndef __DRM_GEM_ATOMIC_HELPER_H__
#define __DRM_GEM_ATOMIC_HELPER_H__
#include <linux/dma-buf-map.h>
#include <linux/iosys-map.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_plane.h>
@ -59,7 +59,7 @@ struct drm_shadow_plane_state {
* The memory mappings stored in map should be established in the plane's
* prepare_fb callback and removed in the cleanup_fb callback.
*/
struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
struct iosys_map map[DRM_FORMAT_MAX_PLANES];
/**
* @data: Address of each framebuffer BO's data
@ -67,7 +67,7 @@ struct drm_shadow_plane_state {
* The address of the data stored in each mapping. This is different
* for framebuffers with non-zero offset fields.
*/
struct dma_buf_map data[DRM_FORMAT_MAX_PLANES];
struct iosys_map data[DRM_FORMAT_MAX_PLANES];
};
/**

6
include/drm/drm_gem_cma_helper.h
View file

@ -38,7 +38,8 @@ void drm_gem_cma_free(struct drm_gem_cma_object *cma_obj);
void drm_gem_cma_print_info(const struct drm_gem_cma_object *cma_obj,
struct drm_printer *p, unsigned int indent);
struct sg_table *drm_gem_cma_get_sg_table(struct drm_gem_cma_object *cma_obj);
int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj, struct dma_buf_map *map);
int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj,
struct iosys_map *map);
int drm_gem_cma_mmap(struct drm_gem_cma_object *cma_obj, struct vm_area_struct *vma);
extern const struct vm_operations_struct drm_gem_cma_vm_ops;
@ -106,7 +107,8 @@ static inline struct sg_table *drm_gem_cma_object_get_sg_table(struct drm_gem_ob
* Returns:
* 0 on success or a negative error code on failure.
*/
static inline int drm_gem_cma_object_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
static inline int drm_gem_cma_object_vmap(struct drm_gem_object *obj,
struct iosys_map *map)
{
struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);

8
include/drm/drm_gem_framebuffer_helper.h
View file

@ -2,7 +2,7 @@
#define __DRM_GEM_FB_HELPER_H__
#include <linux/dma-buf.h>
#include <linux/dma-buf-map.h>
#include <linux/iosys-map.h>
#include <drm/drm_fourcc.h>
@ -40,10 +40,10 @@ drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd);
int drm_gem_fb_vmap(struct drm_framebuffer *fb,
struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES],
struct dma_buf_map data[DRM_FORMAT_MAX_PLANES]);
struct iosys_map map[static DRM_FORMAT_MAX_PLANES],
struct iosys_map data[DRM_FORMAT_MAX_PLANES]);
void drm_gem_fb_vunmap(struct drm_framebuffer *fb,
struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES]);
struct iosys_map map[static DRM_FORMAT_MAX_PLANES]);
int drm_gem_fb_begin_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);
void drm_gem_fb_end_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);

14
include/drm/drm_gem_shmem_helper.h
View file

@ -113,8 +113,10 @@ int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem);
void drm_gem_shmem_put_pages(struct drm_gem_shmem_object *shmem);
int drm_gem_shmem_pin(struct drm_gem_shmem_object *shmem);
void drm_gem_shmem_unpin(struct drm_gem_shmem_object *shmem);
int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map);
void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map);
int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem,
struct iosys_map *map);
void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem,
struct iosys_map *map);
int drm_gem_shmem_mmap(struct drm_gem_shmem_object *shmem, struct vm_area_struct *vma);
int drm_gem_shmem_madvise(struct drm_gem_shmem_object *shmem, int madv);
@ -135,6 +137,8 @@ struct sg_table *drm_gem_shmem_get_pages_sgt(struct drm_gem_shmem_object *shmem)
void drm_gem_shmem_print_info(const struct drm_gem_shmem_object *shmem,
struct drm_printer *p, unsigned int indent);
extern const struct vm_operations_struct drm_gem_shmem_vm_ops;
/*
* GEM object functions
*/
@ -226,7 +230,8 @@ static inline struct sg_table *drm_gem_shmem_object_get_sg_table(struct drm_gem_
* Returns:
* 0 on success or a negative error code on failure.
*/
static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj,
struct iosys_map *map)
{
struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
@ -241,7 +246,8 @@ static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj, struct d
* This function wraps drm_gem_shmem_vunmap(). Drivers that employ the shmem helpers should
* use it as their &drm_gem_object_funcs.vunmap handler.
*/
static inline void drm_gem_shmem_object_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
static inline void drm_gem_shmem_object_vunmap(struct drm_gem_object *obj,
struct iosys_map *map)
{
struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);

6
include/drm/drm_gem_ttm_helper.h
View file

@ -10,7 +10,7 @@
#include <drm/ttm/ttm_bo_api.h>
#include <drm/ttm/ttm_bo_driver.h>
struct dma_buf_map;
struct iosys_map;
#define drm_gem_ttm_of_gem(gem_obj) \
container_of(gem_obj, struct ttm_buffer_object, base)
@ -18,9 +18,9 @@ struct dma_buf_map;
void drm_gem_ttm_print_info(struct drm_printer *p, unsigned int indent,
const struct drm_gem_object *gem);
int drm_gem_ttm_vmap(struct drm_gem_object *gem,
struct dma_buf_map *map);
struct iosys_map *map);
void drm_gem_ttm_vunmap(struct drm_gem_object *gem,
struct dma_buf_map *map);
struct iosys_map *map);
int drm_gem_ttm_mmap(struct drm_gem_object *gem,
struct vm_area_struct *vma);

9
include/drm/drm_gem_vram_helper.h
View file

@ -12,7 +12,7 @@
#include <drm/ttm/ttm_bo_driver.h>
#include <linux/container_of.h>
#include <linux/dma-buf-map.h>
#include <linux/iosys-map.h>
struct drm_mode_create_dumb;
struct drm_plane;
@ -51,7 +51,7 @@ struct vm_area_struct;
*/
struct drm_gem_vram_object {
struct ttm_buffer_object bo;
struct dma_buf_map map;
struct iosys_map map;
/**
* @vmap_use_count:
@ -97,8 +97,9 @@ void drm_gem_vram_put(struct drm_gem_vram_object *gbo);
s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo);
int drm_gem_vram_pin(struct drm_gem_vram_object *gbo, unsigned long pl_flag);
int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo);
int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map);
void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map);
int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct iosys_map *map);
void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo,
struct iosys_map *map);
int drm_gem_vram_fill_create_dumb(struct drm_file *file,
struct drm_device *dev,

10
include/drm/drm_mipi_dbi.h
View file

@ -130,6 +130,14 @@ struct mipi_dbi_dev {
* @dbi: MIPI DBI interface
*/
struct mipi_dbi dbi;
/**
* @driver_private: Driver private data.
* Necessary for drivers with private data since devm_drm_dev_alloc()
* can't allocate structures that embed a structure which then again
* embeds drm_device.
*/
void *driver_private;
};
static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm)
@ -194,7 +202,7 @@ int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
#ifdef CONFIG_DEBUG_FS
void mipi_dbi_debugfs_init(struct drm_minor *minor);
#else
#define mipi_dbi_debugfs_init NULL
static inline void mipi_dbi_debugfs_init(struct drm_minor *minor) {}
#endif
#endif /* __LINUX_MIPI_DBI_H */

18
include/drm/drm_mode_config.h
View file

@ -918,20 +918,14 @@ struct drm_mode_config {
bool async_page_flip;
/**
* @allow_fb_modifiers:
* @fb_modifiers_not_supported:
*
* Whether the driver supports fb modifiers in the ADDFB2.1 ioctl call.
* Note that drivers should not set this directly, it is automatically
* set in drm_universal_plane_init().
*
* IMPORTANT:
*
* If this is set the driver must fill out the full implicit modifier
* information in their &drm_mode_config_funcs.fb_create hook for legacy
* userspace which does not set modifiers. Otherwise the GETFB2 ioctl is
* broken for modifier aware userspace.
* When this flag is set, the DRM device will not expose modifier
* support to userspace. This is only used by legacy drivers that infer
* the buffer layout through heuristics without using modifiers. New
* drivers shall not set fhis flag.
*/
bool allow_fb_modifiers;
bool fb_modifiers_not_supported;
/**
* @normalize_zpos:

7
include/drm/drm_mode_object.h
View file

@ -98,6 +98,10 @@ struct drm_object_properties {
* Hence atomic drivers should not use drm_object_property_set_value()
* and drm_object_property_get_value() on mutable objects, i.e. those
* without the DRM_MODE_PROP_IMMUTABLE flag set.
*
* For atomic drivers the default value of properties is stored in this
* array, so drm_object_property_get_default_value can be used to
* retrieve it.
*/
uint64_t values[DRM_OBJECT_MAX_PROPERTY];
};
@ -126,6 +130,9 @@ int drm_object_property_set_value(struct drm_mode_object *obj,
int drm_object_property_get_value(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t *value);
int drm_object_property_get_default_value(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t *val);
void drm_object_attach_property(struct drm_mode_object *obj,
struct drm_property *property,

8
include/drm/drm_modes.h
View file

@ -466,6 +466,8 @@ void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags);
int of_get_drm_display_mode(struct device_node *np,
struct drm_display_mode *dmode, u32 *bus_flags,
int index);
int of_get_drm_panel_display_mode(struct device_node *np,
struct drm_display_mode *dmode, u32 *bus_flags);
#else
static inline int of_get_drm_display_mode(struct device_node *np,
struct drm_display_mode *dmode,
@ -473,6 +475,12 @@ static inline int of_get_drm_display_mode(struct device_node *np,
{
return -EINVAL;
}
static inline int of_get_drm_panel_display_mode(struct device_node *np,
struct drm_display_mode *dmode, u32 *bus_flags)
{
return -EINVAL;
}
#endif
void drm_mode_set_name(struct drm_display_mode *mode);

1
include/drm/drm_modeset_lock.h
View file

@ -34,6 +34,7 @@ struct drm_modeset_lock;
* struct drm_modeset_acquire_ctx - locking context (see ww_acquire_ctx)
* @ww_ctx: base acquire ctx
* @contended: used internally for -EDEADLK handling
* @stack_depot: used internally for contention debugging
* @locked: list of held locks
* @trylock_only: trylock mode used in atomic contexts/panic notifiers
* @interruptible: whether interruptible locking should be used.

125
include/drm/drm_module.h Normal file
View file

@ -0,0 +1,125 @@
/* SPDX-License-Identifier: MIT */
#ifndef DRM_MODULE_H
#define DRM_MODULE_H
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <drm/drm_drv.h>
/**
* DOC: overview
*
* This library provides helpers registering DRM drivers during module
* initialization and shutdown. The provided helpers act like bus-specific
* module helpers, such as module_pci_driver(), but respect additional
* parameters that control DRM driver registration.
*
* Below is an example of initializing a DRM driver for a device on the
* PCI bus.
*
* .. code-block:: c
*
* struct pci_driver my_pci_drv = {
* };
*
* drm_module_pci_driver(my_pci_drv);
*
* The generated code will test if DRM drivers are enabled and register
* the PCI driver my_pci_drv. For more complex module initialization, you
* can still use module_init() and module_exit() in your driver.
*/
/*
* PCI drivers
*/
static inline int __init drm_pci_register_driver(struct pci_driver *pci_drv)
{
if (drm_firmware_drivers_only())
return -ENODEV;
return pci_register_driver(pci_drv);
}
/**
* drm_module_pci_driver - Register a DRM driver for PCI-based devices
* @__pci_drv: the PCI driver structure
*
* Registers a DRM driver for devices on the PCI bus. The helper
* macro behaves like module_pci_driver() but tests the state of
* drm_firmware_drivers_only(). For more complex module initialization,
* use module_init() and module_exit() directly.
*
* Each module may only use this macro once. Calling it replaces
* module_init() and module_exit().
*/
#define drm_module_pci_driver(__pci_drv) \
module_driver(__pci_drv, drm_pci_register_driver, pci_unregister_driver)
static inline int __init
drm_pci_register_driver_if_modeset(struct pci_driver *pci_drv, int modeset)
{
if (drm_firmware_drivers_only() && modeset == -1)
return -ENODEV;
if (modeset == 0)
return -ENODEV;
return pci_register_driver(pci_drv);
}
static inline void __exit
drm_pci_unregister_driver_if_modeset(struct pci_driver *pci_drv, int modeset)
{
pci_unregister_driver(pci_drv);
}
/**
* drm_module_pci_driver_if_modeset - Register a DRM driver for PCI-based devices
* @__pci_drv: the PCI driver structure
* @__modeset: an additional parameter that disables the driver
*
* This macro is deprecated and only provided for existing drivers. For
* new drivers, use drm_module_pci_driver().
*
* Registers a DRM driver for devices on the PCI bus. The helper macro
* behaves like drm_module_pci_driver() with an additional driver-specific
* flag. If __modeset is 0, the driver has been disabled, if __modeset is
* -1 the driver state depends on the global DRM state. For all other
* values, the PCI driver has been enabled. The default should be -1.
*/
#define drm_module_pci_driver_if_modeset(__pci_drv, __modeset) \
module_driver(__pci_drv, drm_pci_register_driver_if_modeset, \
drm_pci_unregister_driver_if_modeset, __modeset)
/*
* Platform drivers
*/
static inline int __init
drm_platform_driver_register(struct platform_driver *platform_drv)
{
if (drm_firmware_drivers_only())
return -ENODEV;
return platform_driver_register(platform_drv);
}
/**
* drm_module_platform_driver - Register a DRM driver for platform devices
* @__platform_drv: the platform driver structure
*
* Registers a DRM driver for devices on the platform bus. The helper
* macro behaves like module_platform_driver() but tests the state of
* drm_firmware_drivers_only(). For more complex module initialization,
* use module_init() and module_exit() directly.
*
* Each module may only use this macro once. Calling it replaces
* module_init() and module_exit().
*/
#define drm_module_platform_driver(__platform_drv) \
module_driver(__platform_drv, drm_platform_driver_register, \
platform_driver_unregister)
#endif

8
include/drm/drm_panel.h
View file

@ -29,6 +29,7 @@
#include <linux/list.h>
struct backlight_device;
struct dentry;
struct device_node;
struct drm_connector;
struct drm_device;
@ -125,6 +126,13 @@ struct drm_panel_funcs {
*/
int (*get_timings)(struct drm_panel *panel, unsigned int num_timings,
struct display_timing *timings);
/**
* @debugfs_init:
*
* Allows panels to create panels-specific debugfs files.
*/
void (*debugfs_init)(struct drm_panel *panel, struct dentry *root);
};
/**

5
include/drm/drm_plane.h
View file

@ -516,7 +516,7 @@ struct drm_plane_funcs {
* This optional hook is used for the DRM to determine if the given
* format/modifier combination is valid for the plane. This allows the
* DRM to generate the correct format bitmask (which formats apply to
* which modifier), and to valdiate modifiers at atomic_check time.
* which modifier), and to validate modifiers at atomic_check time.
*
* If not present, then any modifier in the plane's modifier
* list is allowed with any of the plane's formats.
@ -803,6 +803,9 @@ void *__drmm_universal_plane_alloc(struct drm_device *dev,
*
* The @drm_plane_funcs.destroy hook must be NULL.
*
* Drivers that only support the DRM_FORMAT_MOD_LINEAR modifier support may set
* @format_modifiers to NULL. The plane will advertise the linear modifier.
*
* Returns:
* Pointer to new plane, or ERR_PTR on failure.
*/

6
include/drm/drm_prime.h
View file

@ -54,7 +54,7 @@ struct device;
struct dma_buf_export_info;
struct dma_buf;
struct dma_buf_attachment;
struct dma_buf_map;
struct iosys_map;
enum dma_data_direction;
@ -83,8 +83,8 @@ struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach,
void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
struct sg_table *sgt,
enum dma_data_direction dir);
int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map);
void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map);
int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct iosys_map *map);
void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map);
int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma);

13
include/drm/drm_privacy_screen_driver.h
View file

@ -73,10 +73,21 @@ struct drm_privacy_screen {
* for more info.
*/
enum drm_privacy_screen_status hw_state;
/**
* @drvdata: Private data owned by the privacy screen provider
*/
void *drvdata;
};
static inline
void *drm_privacy_screen_get_drvdata(struct drm_privacy_screen *priv)
{
return priv->drvdata;
}
struct drm_privacy_screen *drm_privacy_screen_register(
struct device *parent, const struct drm_privacy_screen_ops *ops);
struct device *parent, const struct drm_privacy_screen_ops *ops,
void *data);
void drm_privacy_screen_unregister(struct drm_privacy_screen *priv);
void drm_privacy_screen_call_notifier_chain(struct drm_privacy_screen *priv);

3
include/drm/gpu_scheduler.h
View file

@ -457,13 +457,14 @@ struct drm_gpu_scheduler {
atomic_t _score;
bool ready;
bool free_guilty;
struct device *dev;
};
int drm_sched_init(struct drm_gpu_scheduler *sched,
const struct drm_sched_backend_ops *ops,
uint32_t hw_submission, unsigned hang_limit,
long timeout, struct workqueue_struct *timeout_wq,
atomic_t *score, const char *name);
atomic_t *score, const char *name, struct device *dev);
void drm_sched_fini(struct drm_gpu_scheduler *sched);
int drm_sched_job_init(struct drm_sched_job *job,

6
include/drm/i915_pciids.h
View file

@ -666,6 +666,12 @@
INTEL_VGA_DEVICE(0x46C2, info), \
INTEL_VGA_DEVICE(0x46C3, info)
/* ADL-N */
#define INTEL_ADLN_IDS(info) \
INTEL_VGA_DEVICE(0x46D0, info), \
INTEL_VGA_DEVICE(0x46D1, info), \
INTEL_VGA_DEVICE(0x46D2, info)
/* RPL-S */
#define INTEL_RPLS_IDS(info) \
INTEL_VGA_DEVICE(0xA780, info), \

10
include/drm/ttm/ttm_bo_api.h
View file

@ -47,7 +47,7 @@ struct ttm_global;
struct ttm_device;
struct dma_buf_map;
struct iosys_map;
struct drm_mm_node;
@ -481,17 +481,17 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map);
* ttm_bo_vmap
*
* @bo: The buffer object.
* @map: pointer to a struct dma_buf_map representing the map.
* @map: pointer to a struct iosys_map representing the map.
*
* Sets up a kernel virtual mapping, using ioremap or vmap to the
* data in the buffer object. The parameter @map returns the virtual
* address as struct dma_buf_map. Unmap the buffer with ttm_bo_vunmap().
* address as struct iosys_map. Unmap the buffer with ttm_bo_vunmap().
*
* Returns
* -ENOMEM: Out of memory.
* -EINVAL: Invalid range.
*/
int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map);
int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map);
/**
* ttm_bo_vunmap
@ -501,7 +501,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map);
*
* Unmaps a kernel map set up by ttm_bo_vmap().
*/
void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct dma_buf_map *map);
void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map);
/**
* ttm_bo_mmap_obj - mmap memory backed by a ttm buffer object.

10
include/drm/ttm/ttm_kmap_iter.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
struct ttm_kmap_iter;
struct dma_buf_map;
struct iosys_map;
/**
* struct ttm_kmap_iter_ops - Ops structure for a struct
@ -24,22 +24,22 @@ struct ttm_kmap_iter_ops {
* kmap_local semantics.
* @res_iter: Pointer to the struct ttm_kmap_iter representing
* the resource.
* @dmap: The struct dma_buf_map holding the virtual address after
* @dmap: The struct iosys_map holding the virtual address after
* the operation.
* @i: The location within the resource to map. PAGE_SIZE granularity.
*/
void (*map_local)(struct ttm_kmap_iter *res_iter,
struct dma_buf_map *dmap, pgoff_t i);
struct iosys_map *dmap, pgoff_t i);
/**
* unmap_local() - Unmap a PAGE_SIZE part of the resource previously
* mapped using kmap_local.
* @res_iter: Pointer to the struct ttm_kmap_iter representing
* the resource.
* @dmap: The struct dma_buf_map holding the virtual address after
* @dmap: The struct iosys_map holding the virtual address after
* the operation.
*/
void (*unmap_local)(struct ttm_kmap_iter *res_iter,
struct dma_buf_map *dmap);
struct iosys_map *dmap);
bool maps_tt;
};

39
include/drm/ttm/ttm_resource.h
View file

@ -27,7 +27,7 @@
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/dma-buf-map.h>
#include <linux/iosys-map.h>
#include <linux/dma-fence.h>
#include <drm/drm_print.h>
#include <drm/ttm/ttm_caching.h>
@ -41,7 +41,7 @@ struct ttm_resource;
struct ttm_place;
struct ttm_buffer_object;
struct ttm_placement;
struct dma_buf_map;
struct iosys_map;
struct io_mapping;
struct sg_table;
struct scatterlist;
@ -105,11 +105,11 @@ struct ttm_resource_manager_func {
* @use_type: The memory type is enabled.
* @use_tt: If a TT object should be used for the backing store.
* @size: Size of the managed region.
* @bdev: ttm device this manager belongs to
* @func: structure pointer implementing the range manager. See above
* @move_lock: lock for move fence
* static information. bdev::driver::io_mem_free is never used.
* @lru: The lru list for this memory type.
* @move: The fence of the last pipelined move operation.
* @lru: The lru list for this memory type.
*
* This structure is used to identify and manage memory types for a device.
*/
@ -119,20 +119,26 @@ struct ttm_resource_manager {
*/
bool use_type;
bool use_tt;
struct ttm_device *bdev;
uint64_t size;
const struct ttm_resource_manager_func *func;
spinlock_t move_lock;
/*
* Protected by the global->lru_lock.
*/
struct list_head lru[TTM_MAX_BO_PRIORITY];
/*
* Protected by @move_lock.
*/
struct dma_fence *move;
/*
* Protected by the bdev->lru_lock.
*/
struct list_head lru[TTM_MAX_BO_PRIORITY];
/**
* @usage: How much of the resources are used, protected by the
* bdev->lru_lock.
*/
uint64_t usage;
};
/**
@ -160,6 +166,7 @@ struct ttm_bus_placement {
* @mem_type: Resource type of the allocation.
* @placement: Placement flags.
* @bus: Placement on io bus accessible to the CPU
* @bo: weak reference to the BO, protected by ttm_device::lru_lock
*
* Structure indicating the placement and space resources used by a
* buffer object.
@ -170,6 +177,7 @@ struct ttm_resource {
uint32_t mem_type;
uint32_t placement;
struct ttm_bus_placement bus;
struct ttm_buffer_object *bo;
};
/**
@ -207,7 +215,7 @@ struct ttm_kmap_iter_iomap {
*/
struct ttm_kmap_iter_linear_io {
struct ttm_kmap_iter base;
struct dma_buf_map dmap;
struct iosys_map dmap;
bool needs_unmap;
};
@ -261,19 +269,26 @@ ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
void ttm_resource_init(struct ttm_buffer_object *bo,
const struct ttm_place *place,
struct ttm_resource *res);
void ttm_resource_fini(struct ttm_resource_manager *man,
struct ttm_resource *res);
int ttm_resource_alloc(struct ttm_buffer_object *bo,
const struct ttm_place *place,
struct ttm_resource **res);
void ttm_resource_free(struct ttm_buffer_object *bo, struct ttm_resource **res);
bool ttm_resource_compat(struct ttm_resource *res,
struct ttm_placement *placement);
void ttm_resource_set_bo(struct ttm_resource *res,
struct ttm_buffer_object *bo);
void ttm_resource_manager_init(struct ttm_resource_manager *man,
unsigned long p_size);
struct ttm_device *bdev,
uint64_t size);
int ttm_resource_manager_evict_all(struct ttm_device *bdev,
struct ttm_resource_manager *man);
uint64_t ttm_resource_manager_usage(struct ttm_resource_manager *man);
void ttm_resource_manager_debug(struct ttm_resource_manager *man,
struct drm_printer *p);

2
include/dt-bindings/clock/alphascale,asm9260.h
View file

@ -55,7 +55,7 @@
#define CLKID_AHB_I2S1 45
#define CLKID_AHB_MAC1 46
/* devider */
/* divider */
#define CLKID_SYS_CPU 47
#define CLKID_SYS_AHB 48
#define CLKID_SYS_I2S0M 49

93
include/dt-bindings/clock/am3.h
View file

@ -8,99 +8,6 @@
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
/* mpu clocks */
#define AM3_MPU_CLKCTRL_OFFSET 0x4
#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
/* XXX: Compatibility part end */
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)

98
include/dt-bindings/clock/am4.h
View file

@ -8,104 +8,6 @@
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_wkup clocks */
#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
/* mpu clocks */
#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* gfx_l3 clocks */
#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_rtc clocks */
#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_per clocks */
#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
/* XXX: Compatibility part end. */
/* l3s_tsc clocks */
#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)

2
include/dt-bindings/clock/at91.h
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@ -24,6 +24,7 @@
#define PMC_PLLACK 7
#define PMC_PLLBCK 8
#define PMC_AUDIOPLLCK 9
#define PMC_AUDIOPINCK 10
/* SAMA7G5 */
#define PMC_CPUPLL (PMC_MAIN + 1)
@ -35,6 +36,7 @@
#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
#define PMC_ETHPLL (PMC_MAIN + 8)
#define PMC_CPU (PMC_MAIN + 9)
#define PMC_MCK1 (PMC_MAIN + 10)
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */

2
include/dt-bindings/clock/axis,artpec6-clkctrl.h
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@ -2,7 +2,7 @@
/*
* ARTPEC-6 clock controller indexes
*
* Copyright 2016 Axis Comunications AB.
* Copyright 2016 Axis Communications AB.
*/
#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H

3
include/dt-bindings/clock/boston-clock.h
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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Imagination Technologies
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__

14
include/dt-bindings/clock/cirrus,cs2000-cp.h Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2021 Daniel Mack
*/
#ifndef __DT_BINDINGS_CS2000CP_CLK_H
#define __DT_BINDINGS_CS2000CP_CLK_H
#define CS2000CP_AUX_OUTPUT_REF_CLK 0
#define CS2000CP_AUX_OUTPUT_CLK_IN 1
#define CS2000CP_AUX_OUTPUT_CLK_OUT 2
#define CS2000CP_AUX_OUTPUT_PLL_LOCK 3
#endif /* __DT_BINDINGS_CS2000CP_CLK_H */

182
include/dt-bindings/clock/dra7.h
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@ -8,181 +8,6 @@
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
/* vip clocks */
#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* vpe clocks */
#define DRA7_VPE_CLKCTRL_OFFSET 0x60
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
/* l3main1 clocks */
#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
/* dma clocks */
#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
/* l4cfg clocks */
#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* l3instr clocks */
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* iva clocks */
#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* l4per clocks */
#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* XXX: Compatibility part end. */
/* mpu clocks */
#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@ -267,10 +92,17 @@
#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* iva clocks */
#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)

150
include/dt-bindings/clock/fsd-clk.h Normal file
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@ -0,0 +1,150 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2017-2022 Tesla, Inc.
* https://www.tesla.com
*
* The constants defined in this header are being used in dts
* and fsd platform driver.
*/
#ifndef _DT_BINDINGS_CLOCK_FSD_H
#define _DT_BINDINGS_CLOCK_FSD_H
/* CMU */
#define DOUT_CMU_PLL_SHARED0_DIV4 1
#define DOUT_CMU_PERIC_SHARED1DIV36 2
#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
#define DOUT_CMU_PERIC_SHARED0DIV20 4
#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
#define DOUT_CMU_PLL_SHARED0_DIV6 6
#define DOUT_CMU_FSYS0_SHARED1DIV4 7
#define DOUT_CMU_FSYS0_SHARED0DIV4 8
#define DOUT_CMU_FSYS1_SHARED0DIV8 9
#define DOUT_CMU_FSYS1_SHARED0DIV4 10
#define CMU_CPUCL_SWITCH_GATE 11
#define DOUT_CMU_IMEM_TCUCLK 12
#define DOUT_CMU_IMEM_ACLK 13
#define DOUT_CMU_IMEM_DMACLK 14
#define GAT_CMU_FSYS0_SHARED0DIV4 15
#define CMU_NR_CLK 16
/* PERIC */
#define PERIC_SCLK_UART0 1
#define PERIC_PCLK_UART0 2
#define PERIC_SCLK_UART1 3
#define PERIC_PCLK_UART1 4
#define PERIC_DMA0_IPCLKPORT_ACLK 5
#define PERIC_DMA1_IPCLKPORT_ACLK 6
#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
#define PERIC_PCLK_SPI0 9
#define PERIC_SCLK_SPI0 10
#define PERIC_PCLK_SPI1 11
#define PERIC_SCLK_SPI1 12
#define PERIC_PCLK_SPI2 13
#define PERIC_SCLK_SPI2 14
#define PERIC_PCLK_TDM0 15
#define PERIC_PCLK_HSI2C0 16
#define PERIC_PCLK_HSI2C1 17
#define PERIC_PCLK_HSI2C2 18
#define PERIC_PCLK_HSI2C3 19
#define PERIC_PCLK_HSI2C4 20
#define PERIC_PCLK_HSI2C5 21
#define PERIC_PCLK_HSI2C6 22
#define PERIC_PCLK_HSI2C7 23
#define PERIC_MCAN0_IPCLKPORT_CCLK 24
#define PERIC_MCAN0_IPCLKPORT_PCLK 25
#define PERIC_MCAN1_IPCLKPORT_CCLK 26
#define PERIC_MCAN1_IPCLKPORT_PCLK 27
#define PERIC_MCAN2_IPCLKPORT_CCLK 28
#define PERIC_MCAN2_IPCLKPORT_PCLK 29
#define PERIC_MCAN3_IPCLKPORT_CCLK 30
#define PERIC_MCAN3_IPCLKPORT_PCLK 31
#define PERIC_PCLK_ADCIF 32
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
#define PERIC_HCLK_TDM0 40
#define PERIC_PCLK_TDM1 41
#define PERIC_HCLK_TDM1 42
#define PERIC_EQOS_PHYRXCLK_MUX 43
#define PERIC_EQOS_PHYRXCLK 44
#define PERIC_DOUT_RGMII_CLK 45
#define PERIC_NR_CLK 46
/* FSYS0 */
#define UFS0_MPHY_REFCLK_IXTAL24 1
#define UFS0_MPHY_REFCLK_IXTAL26 2
#define UFS1_MPHY_REFCLK_IXTAL24 3
#define UFS1_MPHY_REFCLK_IXTAL26 4
#define UFS0_TOP0_HCLK_BUS 5
#define UFS0_TOP0_ACLK 6
#define UFS0_TOP0_CLK_UNIPRO 7
#define UFS0_TOP0_FMP_CLK 8
#define UFS1_TOP1_HCLK_BUS 9
#define UFS1_TOP1_ACLK 10
#define UFS1_TOP1_CLK_UNIPRO 11
#define UFS1_TOP1_FMP_CLK 12
#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
#define FSYS0_NR_CLK 23
/* FSYS1 */
#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
#define FSYS1_NR_CLK 9
/* IMEM */
#define IMEM_DMA0_IPCLKPORT_ACLK 1
#define IMEM_DMA1_IPCLKPORT_ACLK 2
#define IMEM_WDT0_IPCLKPORT_PCLK 3
#define IMEM_WDT1_IPCLKPORT_PCLK 4
#define IMEM_WDT2_IPCLKPORT_PCLK 5
#define IMEM_MCT_PCLK 6
#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
#define IMEM_NR_CLK 12
/* MFC */
#define MFC_MFC_IPCLKPORT_ACLK 1
#define MFC_NR_CLK 2
/* CAM_CSI */
#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
#define CAM_CSI_NR_CLK 13
#endif /*_DT_BINDINGS_CLOCK_FSD_H */

201
include/dt-bindings/clock/imx93-clock.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Copyright 2022 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
#define IMX93_CLK_DUMMY 0
#define IMX93_CLK_24M 1
#define IMX93_CLK_EXT1 2
#define IMX93_CLK_SYS_PLL_PFD0 3
#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
#define IMX93_CLK_SYS_PLL_PFD1 5
#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
#define IMX93_CLK_SYS_PLL_PFD2 7
#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
#define IMX93_CLK_AUDIO_PLL 9
#define IMX93_CLK_VIDEO_PLL 10
#define IMX93_CLK_A55_PERIPH 11
#define IMX93_CLK_A55_MTR_BUS 12
#define IMX93_CLK_A55 13
#define IMX93_CLK_M33 14
#define IMX93_CLK_BUS_WAKEUP 15
#define IMX93_CLK_BUS_AON 16
#define IMX93_CLK_WAKEUP_AXI 17
#define IMX93_CLK_SWO_TRACE 18
#define IMX93_CLK_M33_SYSTICK 19
#define IMX93_CLK_FLEXIO1 20
#define IMX93_CLK_FLEXIO2 21
#define IMX93_CLK_LPIT1 22
#define IMX93_CLK_LPIT2 23
#define IMX93_CLK_LPTMR1 24
#define IMX93_CLK_LPTMR2 25
#define IMX93_CLK_TPM1 26
#define IMX93_CLK_TPM2 27
#define IMX93_CLK_TPM3 28
#define IMX93_CLK_TPM4 29
#define IMX93_CLK_TPM5 30
#define IMX93_CLK_TPM6 31
#define IMX93_CLK_FLEXSPI1 32
#define IMX93_CLK_CAN1 33
#define IMX93_CLK_CAN2 34
#define IMX93_CLK_LPUART1 35
#define IMX93_CLK_LPUART2 36
#define IMX93_CLK_LPUART3 37
#define IMX93_CLK_LPUART4 38
#define IMX93_CLK_LPUART5 39
#define IMX93_CLK_LPUART6 40
#define IMX93_CLK_LPUART7 41
#define IMX93_CLK_LPUART8 42
#define IMX93_CLK_LPI2C1 43
#define IMX93_CLK_LPI2C2 44
#define IMX93_CLK_LPI2C3 45
#define IMX93_CLK_LPI2C4 46
#define IMX93_CLK_LPI2C5 47
#define IMX93_CLK_LPI2C6 48
#define IMX93_CLK_LPI2C7 49
#define IMX93_CLK_LPI2C8 50
#define IMX93_CLK_LPSPI1 51
#define IMX93_CLK_LPSPI2 52
#define IMX93_CLK_LPSPI3 53
#define IMX93_CLK_LPSPI4 54
#define IMX93_CLK_LPSPI5 55
#define IMX93_CLK_LPSPI6 56
#define IMX93_CLK_LPSPI7 57
#define IMX93_CLK_LPSPI8 58
#define IMX93_CLK_I3C1 59
#define IMX93_CLK_I3C2 60
#define IMX93_CLK_USDHC1 61
#define IMX93_CLK_USDHC2 62
#define IMX93_CLK_USDHC3 63
#define IMX93_CLK_SAI1 64
#define IMX93_CLK_SAI2 65
#define IMX93_CLK_SAI3 66
#define IMX93_CLK_CCM_CKO1 67
#define IMX93_CLK_CCM_CKO2 68
#define IMX93_CLK_CCM_CKO3 69
#define IMX93_CLK_CCM_CKO4 70
#define IMX93_CLK_HSIO 71
#define IMX93_CLK_HSIO_USB_TEST_60M 72
#define IMX93_CLK_HSIO_ACSCAN_80M 73
#define IMX93_CLK_HSIO_ACSCAN_480M 74
#define IMX93_CLK_ML_APB 75
#define IMX93_CLK_ML 76
#define IMX93_CLK_MEDIA_AXI 77
#define IMX93_CLK_MEDIA_APB 78
#define IMX93_CLK_MEDIA_LDB 79
#define IMX93_CLK_MEDIA_DISP_PIX 80
#define IMX93_CLK_CAM_PIX 81
#define IMX93_CLK_MIPI_TEST_BYTE 82
#define IMX93_CLK_MIPI_PHY_CFG 83
#define IMX93_CLK_ADC 84
#define IMX93_CLK_PDM 85
#define IMX93_CLK_TSTMR1 86
#define IMX93_CLK_TSTMR2 87
#define IMX93_CLK_MQS1 88
#define IMX93_CLK_MQS2 89
#define IMX93_CLK_AUDIO_XCVR 90
#define IMX93_CLK_SPDIF 91
#define IMX93_CLK_ENET 92
#define IMX93_CLK_ENET_TIMER1 93
#define IMX93_CLK_ENET_TIMER2 94
#define IMX93_CLK_ENET_REF 95
#define IMX93_CLK_ENET_REF_PHY 96
#define IMX93_CLK_I3C1_SLOW 97
#define IMX93_CLK_I3C2_SLOW 98
#define IMX93_CLK_USB_PHY_BURUNIN 99
#define IMX93_CLK_PAL_CAME_SCAN 100
#define IMX93_CLK_A55_GATE 101
#define IMX93_CLK_CM33_GATE 102
#define IMX93_CLK_ADC1_GATE 103
#define IMX93_CLK_WDOG1_GATE 104
#define IMX93_CLK_WDOG2_GATE 105
#define IMX93_CLK_WDOG3_GATE 106
#define IMX93_CLK_WDOG4_GATE 107
#define IMX93_CLK_WDOG5_GATE 108
#define IMX93_CLK_SEMA1_GATE 109
#define IMX93_CLK_SEMA2_GATE 110
#define IMX93_CLK_MU_A_GATE 111
#define IMX93_CLK_MU_B_GATE 112
#define IMX93_CLK_EDMA1_GATE 113
#define IMX93_CLK_EDMA2_GATE 114
#define IMX93_CLK_FLEXSPI1_GATE 115
#define IMX93_CLK_GPIO1_GATE 116
#define IMX93_CLK_GPIO2_GATE 117
#define IMX93_CLK_GPIO3_GATE 118
#define IMX93_CLK_GPIO4_GATE 119
#define IMX93_CLK_FLEXIO1_GATE 120
#define IMX93_CLK_FLEXIO2_GATE 121
#define IMX93_CLK_LPIT1_GATE 122
#define IMX93_CLK_LPIT2_GATE 123
#define IMX93_CLK_LPTMR1_GATE 124
#define IMX93_CLK_LPTMR2_GATE 125
#define IMX93_CLK_TPM1_GATE 126
#define IMX93_CLK_TPM2_GATE 127
#define IMX93_CLK_TPM3_GATE 128
#define IMX93_CLK_TPM4_GATE 129
#define IMX93_CLK_TPM5_GATE 130
#define IMX93_CLK_TPM6_GATE 131
#define IMX93_CLK_CAN1_GATE 132
#define IMX93_CLK_CAN2_GATE 133
#define IMX93_CLK_LPUART1_GATE 134
#define IMX93_CLK_LPUART2_GATE 135
#define IMX93_CLK_LPUART3_GATE 136
#define IMX93_CLK_LPUART4_GATE 137
#define IMX93_CLK_LPUART5_GATE 138
#define IMX93_CLK_LPUART6_GATE 139
#define IMX93_CLK_LPUART7_GATE 140
#define IMX93_CLK_LPUART8_GATE 141
#define IMX93_CLK_LPI2C1_GATE 142
#define IMX93_CLK_LPI2C2_GATE 143
#define IMX93_CLK_LPI2C3_GATE 144
#define IMX93_CLK_LPI2C4_GATE 145
#define IMX93_CLK_LPI2C5_GATE 146
#define IMX93_CLK_LPI2C6_GATE 147
#define IMX93_CLK_LPI2C7_GATE 148
#define IMX93_CLK_LPI2C8_GATE 149
#define IMX93_CLK_LPSPI1_GATE 150
#define IMX93_CLK_LPSPI2_GATE 151
#define IMX93_CLK_LPSPI3_GATE 152
#define IMX93_CLK_LPSPI4_GATE 153
#define IMX93_CLK_LPSPI5_GATE 154
#define IMX93_CLK_LPSPI6_GATE 155
#define IMX93_CLK_LPSPI7_GATE 156
#define IMX93_CLK_LPSPI8_GATE 157
#define IMX93_CLK_I3C1_GATE 158
#define IMX93_CLK_I3C2_GATE 159
#define IMX93_CLK_USDHC1_GATE 160
#define IMX93_CLK_USDHC2_GATE 161
#define IMX93_CLK_USDHC3_GATE 162
#define IMX93_CLK_SAI1_GATE 163
#define IMX93_CLK_SAI2_GATE 164
#define IMX93_CLK_SAI3_GATE 165
#define IMX93_CLK_MIPI_CSI_GATE 166
#define IMX93_CLK_MIPI_DSI_GATE 167
#define IMX93_CLK_LVDS_GATE 168
#define IMX93_CLK_LCDIF_GATE 169
#define IMX93_CLK_PXP_GATE 170
#define IMX93_CLK_ISI_GATE 171
#define IMX93_CLK_NIC_MEDIA_GATE 172
#define IMX93_CLK_USB_CONTROLLER_GATE 173
#define IMX93_CLK_USB_TEST_60M_GATE 174
#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
#define IMX93_CLK_PDM_GATE 176
#define IMX93_CLK_MQS1_GATE 177
#define IMX93_CLK_MQS2_GATE 178
#define IMX93_CLK_AUD_XCVR_GATE 179
#define IMX93_CLK_SPDIF_GATE 180
#define IMX93_CLK_HSIO_32K_GATE 181
#define IMX93_CLK_ENET1_GATE 182
#define IMX93_CLK_ENET_QOS_GATE 183
#define IMX93_CLK_SYS_CNT_GATE 184
#define IMX93_CLK_TSTMR1_GATE 185
#define IMX93_CLK_TSTMR2_GATE 186
#define IMX93_CLK_TMC_GATE 187
#define IMX93_CLK_PMRO_GATE 188
#define IMX93_CLK_32K 189
#define IMX93_CLK_END 190
#endif

72
include/dt-bindings/clock/imxrt1050-clock.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright(C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
#define __DT_BINDINGS_CLOCK_IMXRT1050_H
#define IMXRT1050_CLK_DUMMY 0
#define IMXRT1050_CLK_CKIL 1
#define IMXRT1050_CLK_CKIH 2
#define IMXRT1050_CLK_OSC 3
#define IMXRT1050_CLK_PLL2_PFD0_352M 4
#define IMXRT1050_CLK_PLL2_PFD1_594M 5
#define IMXRT1050_CLK_PLL2_PFD2_396M 6
#define IMXRT1050_CLK_PLL3_PFD0_720M 7
#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
#define IMXRT1050_CLK_PLL2_198M 11
#define IMXRT1050_CLK_PLL3_120M 12
#define IMXRT1050_CLK_PLL3_80M 13
#define IMXRT1050_CLK_PLL3_60M 14
#define IMXRT1050_CLK_PLL1_BYPASS 15
#define IMXRT1050_CLK_PLL2_BYPASS 16
#define IMXRT1050_CLK_PLL3_BYPASS 17
#define IMXRT1050_CLK_PLL5_BYPASS 19
#define IMXRT1050_CLK_PLL1_REF_SEL 20
#define IMXRT1050_CLK_PLL2_REF_SEL 21
#define IMXRT1050_CLK_PLL3_REF_SEL 22
#define IMXRT1050_CLK_PLL5_REF_SEL 23
#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
#define IMXRT1050_CLK_PERIPH_SEL 25
#define IMXRT1050_CLK_SEMC_ALT_SEL 26
#define IMXRT1050_CLK_SEMC_SEL 27
#define IMXRT1050_CLK_USDHC1_SEL 28
#define IMXRT1050_CLK_USDHC2_SEL 29
#define IMXRT1050_CLK_LPUART_SEL 30
#define IMXRT1050_CLK_LCDIF_SEL 31
#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
#define IMXRT1050_CLK_VIDEO_DIV 33
#define IMXRT1050_CLK_ARM_PODF 34
#define IMXRT1050_CLK_LPUART_PODF 35
#define IMXRT1050_CLK_USDHC1_PODF 36
#define IMXRT1050_CLK_USDHC2_PODF 37
#define IMXRT1050_CLK_SEMC_PODF 38
#define IMXRT1050_CLK_AHB_PODF 39
#define IMXRT1050_CLK_LCDIF_PRED 40
#define IMXRT1050_CLK_LCDIF_PODF 41
#define IMXRT1050_CLK_USDHC1 42
#define IMXRT1050_CLK_USDHC2 43
#define IMXRT1050_CLK_LPUART1 44
#define IMXRT1050_CLK_SEMC 45
#define IMXRT1050_CLK_LCDIF_APB 46
#define IMXRT1050_CLK_PLL1_ARM 47
#define IMXRT1050_CLK_PLL2_SYS 48
#define IMXRT1050_CLK_PLL3_USB_OTG 49
#define IMXRT1050_CLK_PLL4_AUDIO 50
#define IMXRT1050_CLK_PLL5_VIDEO 51
#define IMXRT1050_CLK_PLL6_ENET 52
#define IMXRT1050_CLK_PLL7_USB_HOST 53
#define IMXRT1050_CLK_LCDIF_PIX 54
#define IMXRT1050_CLK_USBOH3 55
#define IMXRT1050_CLK_IPG_PDOF 56
#define IMXRT1050_CLK_PER_CLK_SEL 57
#define IMXRT1050_CLK_PER_PDOF 58
#define IMXRT1050_CLK_DMA 59
#define IMXRT1050_CLK_DMA_MUX 60
#define IMXRT1050_CLK_END 61
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */

4
include/dt-bindings/clock/marvell,mmp2.h
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@ -32,7 +32,7 @@
#define MMP2_CLK_I2S0 31
#define MMP2_CLK_I2S1 32
/* apb periphrals */
/* apb peripherals */
#define MMP2_CLK_TWSI0 60
#define MMP2_CLK_TWSI1 61
#define MMP2_CLK_TWSI2 62
@ -60,7 +60,7 @@
#define MMP3_CLK_THERMAL2 84
#define MMP3_CLK_THERMAL3 85
/* axi periphrals */
/* axi peripherals */
#define MMP2_CLK_SDH0 101
#define MMP2_CLK_SDH1 102
#define MMP2_CLK_SDH2 103

4
include/dt-bindings/clock/marvell,pxa168.h
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@ -23,7 +23,7 @@
#define PXA168_CLK_UART_PLL 27
#define PXA168_CLK_USB_PLL 28
/* apb periphrals */
/* apb peripherals */
#define PXA168_CLK_TWSI0 60
#define PXA168_CLK_TWSI1 61
#define PXA168_CLK_TWSI2 62
@ -45,7 +45,7 @@
#define PXA168_CLK_SSP4 78
#define PXA168_CLK_TIMER 79
/* axi periphrals */
/* axi peripherals */
#define PXA168_CLK_DFC 100
#define PXA168_CLK_SDH0 101
#define PXA168_CLK_SDH1 102

4
include/dt-bindings/clock/marvell,pxa910.h
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@ -23,7 +23,7 @@
#define PXA910_CLK_UART_PLL 27
#define PXA910_CLK_USB_PLL 28
/* apb periphrals */
/* apb peripherals */
#define PXA910_CLK_TWSI0 60
#define PXA910_CLK_TWSI1 61
#define PXA910_CLK_TWSI2 62
@ -43,7 +43,7 @@
#define PXA910_CLK_TIMER0 76
#define PXA910_CLK_TIMER1 77
/* axi periphrals */
/* axi peripherals */
#define PXA910_CLK_DFC 100
#define PXA910_CLK_SDH0 101
#define PXA910_CLK_SDH1 102

45
include/dt-bindings/clock/microchip,mpfs-clock.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Daire McNamara,<daire.mcnamara@microchip.com>
* Copyright (C) 2020 Microchip Technology Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
#define CLK_CPU 0
#define CLK_AXI 1
#define CLK_AHB 2
#define CLK_ENVM 3
#define CLK_MAC0 4
#define CLK_MAC1 5
#define CLK_MMC 6
#define CLK_TIMER 7
#define CLK_MMUART0 8
#define CLK_MMUART1 9
#define CLK_MMUART2 10
#define CLK_MMUART3 11
#define CLK_MMUART4 12
#define CLK_SPI0 13
#define CLK_SPI1 14
#define CLK_I2C0 15
#define CLK_I2C1 16
#define CLK_CAN0 17
#define CLK_CAN1 18
#define CLK_USB 19
#define CLK_RESERVED 20
#define CLK_RTC 21
#define CLK_QSPI 22
#define CLK_GPIO0 23
#define CLK_GPIO1 24
#define CLK_GPIO2 25
#define CLK_DDRC 26
#define CLK_FIC0 27
#define CLK_FIC1 28
#define CLK_FIC2 29
#define CLK_FIC3 30
#define CLK_ATHENA 31
#define CLK_CFM 32
#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */

2
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Nuvoton NPCM7xx Clock Generator binding
* clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
* clock binding number for all clocks supported by nuvoton,npcm7xx-clk
*
* Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
*

34
include/dt-bindings/clock/qcom,dispcc-qcm2290.h Normal file
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@ -0,0 +1,34 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_ESC0_CLK 7
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
#define DISP_CC_MDSS_MDP_CLK 9
#define DISP_CC_MDSS_MDP_CLK_SRC 10
#define DISP_CC_MDSS_MDP_LUT_CLK 11
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12
#define DISP_CC_MDSS_PCLK0_CLK 13
#define DISP_CC_MDSS_PCLK0_CLK_SRC 14
#define DISP_CC_MDSS_VSYNC_CLK 15
#define DISP_CC_MDSS_VSYNC_CLK_SRC 16
#define DISP_CC_SLEEP_CLK 17
#define DISP_CC_SLEEP_CLK_SRC 18
#define DISP_CC_XO_CLK 19
#define DISP_CC_XO_CLK_SRC 20
#define MDSS_GDSC 0
#endif

41
include/dt-bindings/clock/qcom,dispcc-sm6125.h Normal file
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@ -0,0 +1,41 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
#define DISP_CC_PLL0 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
#define DISP_CC_MDSS_DP_AUX_CLK 6
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7
#define DISP_CC_MDSS_DP_CRYPTO_CLK 8
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9
#define DISP_CC_MDSS_DP_LINK_CLK 10
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 12
#define DISP_CC_MDSS_DP_PIXEL_CLK 13
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 14
#define DISP_CC_MDSS_ESC0_CLK 15
#define DISP_CC_MDSS_ESC0_CLK_SRC 16
#define DISP_CC_MDSS_MDP_CLK 17
#define DISP_CC_MDSS_MDP_CLK_SRC 18
#define DISP_CC_MDSS_MDP_LUT_CLK 19
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 20
#define DISP_CC_MDSS_PCLK0_CLK 21
#define DISP_CC_MDSS_PCLK0_CLK_SRC 22
#define DISP_CC_MDSS_ROT_CLK 23
#define DISP_CC_MDSS_ROT_CLK_SRC 24
#define DISP_CC_MDSS_VSYNC_CLK 25
#define DISP_CC_MDSS_VSYNC_CLK_SRC 26
#define DISP_CC_XO_CLK 27
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#endif

48
include/dt-bindings/clock/qcom,dispcc-sm6350.h Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_DP_AUX_CLK 7
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
#define DISP_CC_MDSS_DP_LINK_CLK 11
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
#define DISP_CC_MDSS_DP_PIXEL_CLK 15
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
#define DISP_CC_MDSS_ESC0_CLK 17
#define DISP_CC_MDSS_ESC0_CLK_SRC 18
#define DISP_CC_MDSS_MDP_CLK 19
#define DISP_CC_MDSS_MDP_CLK_SRC 20
#define DISP_CC_MDSS_MDP_LUT_CLK 21
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22
#define DISP_CC_MDSS_PCLK0_CLK 23
#define DISP_CC_MDSS_PCLK0_CLK_SRC 24
#define DISP_CC_MDSS_ROT_CLK 25
#define DISP_CC_MDSS_ROT_CLK_SRC 26
#define DISP_CC_MDSS_RSCC_AHB_CLK 27
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28
#define DISP_CC_MDSS_VSYNC_CLK 29
#define DISP_CC_MDSS_VSYNC_CLK_SRC 30
#define DISP_CC_SLEEP_CLK 31
#define DISP_CC_XO_CLK 32
/* GDSCs */
#define MDSS_GDSC 0
#endif

5
include/dt-bindings/clock/qcom,gcc-ipq806x.h
View file

@ -240,7 +240,7 @@
#define PLL14 232
#define PLL14_VOTE 233
#define PLL18 234
#define CE5_SRC 235
#define CE5_A_CLK 235
#define CE5_H_CLK 236
#define CE5_CORE_CLK 237
#define CE3_SLEEP_CLK 238
@ -283,5 +283,8 @@
#define EBI2_AON_CLK 281
#define NSSTCM_CLK_SRC 282
#define NSSTCM_CLK 283
#define CE5_A_CLK_SRC 285
#define CE5_H_CLK_SRC 286
#define CE5_CORE_CLK_SRC 287
#endif

5
include/dt-bindings/clock/qcom,gcc-sm8150.h
View file

@ -241,7 +241,12 @@
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
/* GCC GDSCRs */
#define PCIE_0_GDSC 0
#define PCIE_1_GDSC 1
#define UFS_CARD_GDSC 2
#define UFS_PHY_GDSC 3
#define USB30_PRIM_GDSC 4
#define USB30_SEC_GDSC 5
#define EMAC_GDSC 6
#endif

37
include/dt-bindings/clock/qcom,gpucc-sm6350.h Normal file
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@ -0,0 +1,37 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_ACD_AHB_CLK 2
#define GPU_CC_ACD_CXO_CLK 3
#define GPU_CC_AHB_CLK 4
#define GPU_CC_CRC_AHB_CLK 5
#define GPU_CC_CX_GFX3D_CLK 6
#define GPU_CC_CX_GFX3D_SLV_CLK 7
#define GPU_CC_CX_GMU_CLK 8
#define GPU_CC_CX_SNOC_DVM_CLK 9
#define GPU_CC_CXO_AON_CLK 10
#define GPU_CC_CXO_CLK 11
#define GPU_CC_GMU_CLK_SRC 12
#define GPU_CC_GX_CXO_CLK 13
#define GPU_CC_GX_GFX3D_CLK 14
#define GPU_CC_GX_GFX3D_CLK_SRC 15
#define GPU_CC_GX_GMU_CLK 16
#define GPU_CC_GX_VSENSE_CLK 17
/* CLK_HW */
#define GPU_CC_CRC_DIV 0
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

2
include/dt-bindings/clock/qcom,rpmcc.h
View file

@ -165,5 +165,7 @@
#define RPM_SMD_PKA_A_CLK 119
#define RPM_SMD_CPUSS_GNOC_CLK 120
#define RPM_SMD_CPUSS_GNOC_A_CLK 121
#define RPM_SMD_MSS_CFG_AHB_CLK 122
#define RPM_SMD_MSS_CFG_AHB_A_CLK 123
#endif

1
include/dt-bindings/clock/r9a06g032-sysctrl.h
View file

@ -74,6 +74,7 @@
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
#define R9A06G032_HCLK_CAN0 85
#define R9A06G032_HCLK_CAN1 86

229
include/dt-bindings/clock/r9a07g054-cpg.h Normal file
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@ -0,0 +1,229 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G054 CPG Core Clocks */
#define R9A07G054_CLK_I 0
#define R9A07G054_CLK_I2 1
#define R9A07G054_CLK_G 2
#define R9A07G054_CLK_S0 3
#define R9A07G054_CLK_S1 4
#define R9A07G054_CLK_SPI0 5
#define R9A07G054_CLK_SPI1 6
#define R9A07G054_CLK_SD0 7
#define R9A07G054_CLK_SD1 8
#define R9A07G054_CLK_M0 9
#define R9A07G054_CLK_M1 10
#define R9A07G054_CLK_M2 11
#define R9A07G054_CLK_M3 12
#define R9A07G054_CLK_M4 13
#define R9A07G054_CLK_HP 14
#define R9A07G054_CLK_TSU 15
#define R9A07G054_CLK_ZT 16
#define R9A07G054_CLK_P0 17
#define R9A07G054_CLK_P1 18
#define R9A07G054_CLK_P2 19
#define R9A07G054_CLK_AT 20
#define R9A07G054_OSCCLK 21
#define R9A07G054_CLK_P0_DIV2 22
#define R9A07G054_CLK_DRP_M 23
#define R9A07G054_CLK_DRP_D 24
#define R9A07G054_CLK_DRP_A 25
/* R9A07G054 Module Clocks */
#define R9A07G054_CA55_SCLK 0
#define R9A07G054_CA55_PCLK 1
#define R9A07G054_CA55_ATCLK 2
#define R9A07G054_CA55_GICCLK 3
#define R9A07G054_CA55_PERICLK 4
#define R9A07G054_CA55_ACLK 5
#define R9A07G054_CA55_TSCLK 6
#define R9A07G054_GIC600_GICCLK 7
#define R9A07G054_IA55_CLK 8
#define R9A07G054_IA55_PCLK 9
#define R9A07G054_MHU_PCLK 10
#define R9A07G054_SYC_CNT_CLK 11
#define R9A07G054_DMAC_ACLK 12
#define R9A07G054_DMAC_PCLK 13
#define R9A07G054_OSTM0_PCLK 14
#define R9A07G054_OSTM1_PCLK 15
#define R9A07G054_OSTM2_PCLK 16
#define R9A07G054_MTU_X_MCK_MTU3 17
#define R9A07G054_POE3_CLKM_POE 18
#define R9A07G054_GPT_PCLK 19
#define R9A07G054_POEG_A_CLKP 20
#define R9A07G054_POEG_B_CLKP 21
#define R9A07G054_POEG_C_CLKP 22
#define R9A07G054_POEG_D_CLKP 23
#define R9A07G054_WDT0_PCLK 24
#define R9A07G054_WDT0_CLK 25
#define R9A07G054_WDT1_PCLK 26
#define R9A07G054_WDT1_CLK 27
#define R9A07G054_WDT2_PCLK 28
#define R9A07G054_WDT2_CLK 29
#define R9A07G054_SPI_CLK2 30
#define R9A07G054_SPI_CLK 31
#define R9A07G054_SDHI0_IMCLK 32
#define R9A07G054_SDHI0_IMCLK2 33
#define R9A07G054_SDHI0_CLK_HS 34
#define R9A07G054_SDHI0_ACLK 35
#define R9A07G054_SDHI1_IMCLK 36
#define R9A07G054_SDHI1_IMCLK2 37
#define R9A07G054_SDHI1_CLK_HS 38
#define R9A07G054_SDHI1_ACLK 39
#define R9A07G054_GPU_CLK 40
#define R9A07G054_GPU_AXI_CLK 41
#define R9A07G054_GPU_ACE_CLK 42
#define R9A07G054_ISU_ACLK 43
#define R9A07G054_ISU_PCLK 44
#define R9A07G054_H264_CLK_A 45
#define R9A07G054_H264_CLK_P 46
#define R9A07G054_CRU_SYSCLK 47
#define R9A07G054_CRU_VCLK 48
#define R9A07G054_CRU_PCLK 49
#define R9A07G054_CRU_ACLK 50
#define R9A07G054_MIPI_DSI_PLLCLK 51
#define R9A07G054_MIPI_DSI_SYSCLK 52
#define R9A07G054_MIPI_DSI_ACLK 53
#define R9A07G054_MIPI_DSI_PCLK 54
#define R9A07G054_MIPI_DSI_VCLK 55
#define R9A07G054_MIPI_DSI_LPCLK 56
#define R9A07G054_LCDC_CLK_A 57
#define R9A07G054_LCDC_CLK_P 58
#define R9A07G054_LCDC_CLK_D 59
#define R9A07G054_SSI0_PCLK2 60
#define R9A07G054_SSI0_PCLK_SFR 61
#define R9A07G054_SSI1_PCLK2 62
#define R9A07G054_SSI1_PCLK_SFR 63
#define R9A07G054_SSI2_PCLK2 64
#define R9A07G054_SSI2_PCLK_SFR 65
#define R9A07G054_SSI3_PCLK2 66
#define R9A07G054_SSI3_PCLK_SFR 67
#define R9A07G054_SRC_CLKP 68
#define R9A07G054_USB_U2H0_HCLK 69
#define R9A07G054_USB_U2H1_HCLK 70
#define R9A07G054_USB_U2P_EXR_CPUCLK 71
#define R9A07G054_USB_PCLK 72
#define R9A07G054_ETH0_CLK_AXI 73
#define R9A07G054_ETH0_CLK_CHI 74
#define R9A07G054_ETH1_CLK_AXI 75
#define R9A07G054_ETH1_CLK_CHI 76
#define R9A07G054_I2C0_PCLK 77
#define R9A07G054_I2C1_PCLK 78
#define R9A07G054_I2C2_PCLK 79
#define R9A07G054_I2C3_PCLK 80
#define R9A07G054_SCIF0_CLK_PCK 81
#define R9A07G054_SCIF1_CLK_PCK 82
#define R9A07G054_SCIF2_CLK_PCK 83
#define R9A07G054_SCIF3_CLK_PCK 84
#define R9A07G054_SCIF4_CLK_PCK 85
#define R9A07G054_SCI0_CLKP 86
#define R9A07G054_SCI1_CLKP 87
#define R9A07G054_IRDA_CLKP 88
#define R9A07G054_RSPI0_CLKB 89
#define R9A07G054_RSPI1_CLKB 90
#define R9A07G054_RSPI2_CLKB 91
#define R9A07G054_CANFD_PCLK 92
#define R9A07G054_GPIO_HCLK 93
#define R9A07G054_ADC_ADCLK 94
#define R9A07G054_ADC_PCLK 95
#define R9A07G054_TSU_PCLK 96
#define R9A07G054_STPAI_INITCLK 97
#define R9A07G054_STPAI_ACLK 98
#define R9A07G054_STPAI_MCLK 99
#define R9A07G054_STPAI_DCLKIN 100
#define R9A07G054_STPAI_ACLK_DRP 101
/* R9A07G054 Resets */
#define R9A07G054_CA55_RST_1_0 0
#define R9A07G054_CA55_RST_1_1 1
#define R9A07G054_CA55_RST_3_0 2
#define R9A07G054_CA55_RST_3_1 3
#define R9A07G054_CA55_RST_4 4
#define R9A07G054_CA55_RST_5 5
#define R9A07G054_CA55_RST_6 6
#define R9A07G054_CA55_RST_7 7
#define R9A07G054_CA55_RST_8 8
#define R9A07G054_CA55_RST_9 9
#define R9A07G054_CA55_RST_10 10
#define R9A07G054_CA55_RST_11 11
#define R9A07G054_CA55_RST_12 12
#define R9A07G054_GIC600_GICRESET_N 13
#define R9A07G054_GIC600_DBG_GICRESET_N 14
#define R9A07G054_IA55_RESETN 15
#define R9A07G054_MHU_RESETN 16
#define R9A07G054_DMAC_ARESETN 17
#define R9A07G054_DMAC_RST_ASYNC 18
#define R9A07G054_SYC_RESETN 19
#define R9A07G054_OSTM0_PRESETZ 20
#define R9A07G054_OSTM1_PRESETZ 21
#define R9A07G054_OSTM2_PRESETZ 22
#define R9A07G054_MTU_X_PRESET_MTU3 23
#define R9A07G054_POE3_RST_M_REG 24
#define R9A07G054_GPT_RST_C 25
#define R9A07G054_POEG_A_RST 26
#define R9A07G054_POEG_B_RST 27
#define R9A07G054_POEG_C_RST 28
#define R9A07G054_POEG_D_RST 29
#define R9A07G054_WDT0_PRESETN 30
#define R9A07G054_WDT1_PRESETN 31
#define R9A07G054_WDT2_PRESETN 32
#define R9A07G054_SPI_RST 33
#define R9A07G054_SDHI0_IXRST 34
#define R9A07G054_SDHI1_IXRST 35
#define R9A07G054_GPU_RESETN 36
#define R9A07G054_GPU_AXI_RESETN 37
#define R9A07G054_GPU_ACE_RESETN 38
#define R9A07G054_ISU_ARESETN 39
#define R9A07G054_ISU_PRESETN 40
#define R9A07G054_H264_X_RESET_VCP 41
#define R9A07G054_H264_CP_PRESET_P 42
#define R9A07G054_CRU_CMN_RSTB 43
#define R9A07G054_CRU_PRESETN 44
#define R9A07G054_CRU_ARESETN 45
#define R9A07G054_MIPI_DSI_CMN_RSTB 46
#define R9A07G054_MIPI_DSI_ARESET_N 47
#define R9A07G054_MIPI_DSI_PRESET_N 48
#define R9A07G054_LCDC_RESET_N 49
#define R9A07G054_SSI0_RST_M2_REG 50
#define R9A07G054_SSI1_RST_M2_REG 51
#define R9A07G054_SSI2_RST_M2_REG 52
#define R9A07G054_SSI3_RST_M2_REG 53
#define R9A07G054_SRC_RST 54
#define R9A07G054_USB_U2H0_HRESETN 55
#define R9A07G054_USB_U2H1_HRESETN 56
#define R9A07G054_USB_U2P_EXL_SYSRST 57
#define R9A07G054_USB_PRESETN 58
#define R9A07G054_ETH0_RST_HW_N 59
#define R9A07G054_ETH1_RST_HW_N 60
#define R9A07G054_I2C0_MRST 61
#define R9A07G054_I2C1_MRST 62
#define R9A07G054_I2C2_MRST 63
#define R9A07G054_I2C3_MRST 64
#define R9A07G054_SCIF0_RST_SYSTEM_N 65
#define R9A07G054_SCIF1_RST_SYSTEM_N 66
#define R9A07G054_SCIF2_RST_SYSTEM_N 67
#define R9A07G054_SCIF3_RST_SYSTEM_N 68
#define R9A07G054_SCIF4_RST_SYSTEM_N 69
#define R9A07G054_SCI0_RST 70
#define R9A07G054_SCI1_RST 71
#define R9A07G054_IRDA_RST 72
#define R9A07G054_RSPI0_RST 73
#define R9A07G054_RSPI1_RST 74
#define R9A07G054_RSPI2_RST 75
#define R9A07G054_CANFD_RSTP_N 76
#define R9A07G054_CANFD_RSTC_N 77
#define R9A07G054_GPIO_RSTN 78
#define R9A07G054_GPIO_PORT_RESETN 79
#define R9A07G054_GPIO_SPARE_RESETN 80
#define R9A07G054_ADC_PRESETN 81
#define R9A07G054_ADC_ADRST_N 82
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */

8
include/dt-bindings/clock/sifive-fu540-prci.h
View file

@ -10,9 +10,9 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_TLCLK 3
#define FU540_PRCI_CLK_COREPLL 0
#define FU540_PRCI_CLK_DDRPLL 1
#define FU540_PRCI_CLK_GEMGXLPLL 2
#define FU540_PRCI_CLK_TLCLK 3
#endif

18
include/dt-bindings/clock/sifive-fu740-prci.h
View file

@ -11,14 +11,14 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_DVFSCOREPLL 3
#define PRCI_CLK_HFPCLKPLL 4
#define PRCI_CLK_CLTXPLL 5
#define PRCI_CLK_TLCLK 6
#define PRCI_CLK_PCLK 7
#define PRCI_CLK_PCIE_AUX 8
#define FU740_PRCI_CLK_COREPLL 0
#define FU740_PRCI_CLK_DDRPLL 1
#define FU740_PRCI_CLK_GEMGXLPLL 2
#define FU740_PRCI_CLK_DVFSCOREPLL 3
#define FU740_PRCI_CLK_HFPCLKPLL 4
#define FU740_PRCI_CLK_CLTXPLL 5
#define FU740_PRCI_CLK_TLCLK 6
#define FU740_PRCI_CLK_PCLK 7
#define FU740_PRCI_CLK_PCIE_AUX 8
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */

41
include/dt-bindings/clock/starfive-jh7100-audio.h Normal file
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@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
#define JH7100_AUDCLK_ADC_MCLK 0
#define JH7100_AUDCLK_I2S1_MCLK 1
#define JH7100_AUDCLK_I2SADC_APB 2
#define JH7100_AUDCLK_I2SADC_BCLK 3
#define JH7100_AUDCLK_I2SADC_BCLK_N 4
#define JH7100_AUDCLK_I2SADC_LRCLK 5
#define JH7100_AUDCLK_PDM_APB 6
#define JH7100_AUDCLK_PDM_MCLK 7
#define JH7100_AUDCLK_I2SVAD_APB 8
#define JH7100_AUDCLK_SPDIF 9
#define JH7100_AUDCLK_SPDIF_APB 10
#define JH7100_AUDCLK_PWMDAC_APB 11
#define JH7100_AUDCLK_DAC_MCLK 12
#define JH7100_AUDCLK_I2SDAC_APB 13
#define JH7100_AUDCLK_I2SDAC_BCLK 14
#define JH7100_AUDCLK_I2SDAC_BCLK_N 15
#define JH7100_AUDCLK_I2SDAC_LRCLK 16
#define JH7100_AUDCLK_I2S1_APB 17
#define JH7100_AUDCLK_I2S1_BCLK 18
#define JH7100_AUDCLK_I2S1_BCLK_N 19
#define JH7100_AUDCLK_I2S1_LRCLK 20
#define JH7100_AUDCLK_I2SDAC16K_APB 21
#define JH7100_AUDCLK_APB0_BUS 22
#define JH7100_AUDCLK_DMA1P_AHB 23
#define JH7100_AUDCLK_USB_APB 24
#define JH7100_AUDCLK_USB_LPM 25
#define JH7100_AUDCLK_USB_STB 26
#define JH7100_AUDCLK_APB_EN 27
#define JH7100_AUDCLK_VAD_MEM 28
#define JH7100_AUDCLK_END 29
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */

4
include/dt-bindings/clock/stm32fx-clock.h
View file

@ -7,10 +7,10 @@
*/
/*
* List of clocks wich are not derived from system clock (SYSCLOCK)
* List of clocks which are not derived from system clock (SYSCLOCK)
*
* The index of these clocks is the secondary index of DT bindings
* (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
* (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
*
* e.g:
<assigned-clocks = <&rcc 1 CLK_LSE>;

2
include/dt-bindings/clock/stratix10-clock.h
View file

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017, Intel Corporation
*/

10
include/dt-bindings/clock/sun6i-rtc.h Normal file
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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
#define CLK_OSC32K 0
#define CLK_OSC32K_FANOUT 1
#define CLK_IOSC 2
#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */

135
include/dt-bindings/clock/tegra234-clock.h
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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
@ -9,6 +9,26 @@
* @defgroup bpmp_clock_ids Clock ID's
* @{
*/
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
#define TEGRA234_CLK_AHUB 4U
/** @brief output of gate CLK_ENB_APB2APE */
#define TEGRA234_CLK_APB2APE 5U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
#define TEGRA234_CLK_APE 6U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
#define TEGRA234_CLK_AUD_MCLK 7U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
#define TEGRA234_CLK_DMIC1 15U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
#define TEGRA234_CLK_DMIC2 16U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
#define TEGRA234_CLK_DMIC3 17U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
#define TEGRA234_CLK_DMIC4 18U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
#define TEGRA234_CLK_DSPK1 29U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
#define TEGRA234_CLK_DSPK2 30U
/**
* @brief controls the EMC clock frequency.
* @details Doing a clk_set_rate on this clock will select the
@ -20,15 +40,126 @@
#define TEGRA234_CLK_EMC 31U
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA234_CLK_FUSE 40U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
#define TEGRA234_CLK_I2C1 48U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
#define TEGRA234_CLK_I2C2 49U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
#define TEGRA234_CLK_I2C3 50U
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
#define TEGRA234_CLK_I2C4 51U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
#define TEGRA234_CLK_I2C6 52U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
#define TEGRA234_CLK_I2C7 53U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
#define TEGRA234_CLK_I2C8 54U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
#define TEGRA234_CLK_I2C9 55U
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
#define TEGRA234_CLK_I2S1 56U
/** @brief clock recovered from I2S1 input */
#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
#define TEGRA234_CLK_I2S2 58U
/** @brief clock recovered from I2S2 input */
#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
#define TEGRA234_CLK_I2S3 60U
/** @brief clock recovered from I2S3 input */
#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
#define TEGRA234_CLK_I2S4 62U
/** @brief clock recovered from I2S4 input */
#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
#define TEGRA234_CLK_I2S5 64U
/** @brief clock recovered from I2S5 input */
#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
#define TEGRA234_CLK_I2S6 66U
/** @brief clock recovered from I2S6 input */
#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
#define TEGRA234_CLK_PLLA 93U
/** @brief PLLP clk output */
#define TEGRA234_CLK_PLLP_OUT0 102U
/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
#define TEGRA234_CLK_PLLA_OUT0 104U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
#define TEGRA234_CLK_PWM1 105U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
#define TEGRA234_CLK_PWM2 106U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
#define TEGRA234_CLK_PWM3 107U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
#define TEGRA234_CLK_PWM4 108U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
#define TEGRA234_CLK_PWM5 109U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
#define TEGRA234_CLK_PWM6 110U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
#define TEGRA234_CLK_PWM7 111U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
#define TEGRA234_CLK_PWM8 112U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
#define TEGRA234_CLK_SYNC_DMIC1 139U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
#define TEGRA234_CLK_SYNC_DMIC2 140U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
#define TEGRA234_CLK_SYNC_DMIC3 141U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
#define TEGRA234_CLK_SYNC_DMIC4 142U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
#define TEGRA234_CLK_SYNC_DSPK1 143U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
#define TEGRA234_CLK_SYNC_DSPK2 144U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
#define TEGRA234_CLK_SYNC_I2S1 145U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
#define TEGRA234_CLK_SYNC_I2S2 146U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
#define TEGRA234_CLK_SYNC_I2S3 147U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
#define TEGRA234_CLK_SYNC_I2S4 148U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
#define TEGRA234_CLK_SYNC_I2S5 149U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
#define TEGRA234_CLK_SYNC_I2S6 150U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA234_CLK_UARTA 155U
/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
#define TEGRA234_CLK_PEX1_C6_CORE 161U
/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
#define TEGRA234_CLK_PEX2_C7_CORE 171U
/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
#define TEGRA234_CLK_PEX2_C8_CORE 172U
/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
#define TEGRA234_CLK_PEX2_C9_CORE 173U
/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
#define TEGRA234_CLK_PEX2_C10_CORE 187U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
#define TEGRA234_CLK_PEX0_C0_CORE 220U
/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
#define TEGRA234_CLK_PEX0_C1_CORE 221U
/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
#define TEGRA234_CLK_PEX0_C2_CORE 222U
/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
#define TEGRA234_CLK_PEX0_C3_CORE 223U
/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
#define TEGRA234_CLK_PEX0_C4_CORE 224U
/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
#define TEGRA234_CLK_PEX1_C5_CORE 225U
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA234_CLK_PLLC4 237U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
#define TEGRA234_CLK_AZA_2XBIT 457U
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
#define TEGRA234_CLK_AZA_BIT 458U
#endif

99
include/dt-bindings/gpio/meson-s4-gpio.h Normal file
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@ -0,0 +1,99 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Qianggui Song <qianggui.song@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_S4_GPIO_H
#define _DT_BINDINGS_MESON_S4_GPIO_H
#define GPIOB_0 0
#define GPIOB_1 1
#define GPIOB_2 2
#define GPIOB_3 3
#define GPIOB_4 4
#define GPIOB_5 5
#define GPIOB_6 6
#define GPIOB_7 7
#define GPIOB_8 8
#define GPIOB_9 9
#define GPIOB_10 10
#define GPIOB_11 11
#define GPIOB_12 12
#define GPIOB_13 13
#define GPIOC_0 14
#define GPIOC_1 15
#define GPIOC_2 16
#define GPIOC_3 17
#define GPIOC_4 18
#define GPIOC_5 19
#define GPIOC_6 20
#define GPIOC_7 21
#define GPIOE_0 22
#define GPIOE_1 23
#define GPIOD_0 24
#define GPIOD_1 25
#define GPIOD_2 26
#define GPIOD_3 27
#define GPIOD_4 28
#define GPIOD_5 29
#define GPIOD_6 30
#define GPIOD_7 31
#define GPIOD_8 32
#define GPIOD_9 33
#define GPIOD_10 34
#define GPIOD_11 35
#define GPIOH_0 36
#define GPIOH_1 37
#define GPIOH_2 38
#define GPIOH_3 39
#define GPIOH_4 40
#define GPIOH_5 41
#define GPIOH_6 42
#define GPIOH_7 43
#define GPIOH_8 44
#define GPIOH_9 45
#define GPIOH_10 46
#define GPIOH_11 47
#define GPIOX_0 48
#define GPIOX_1 49
#define GPIOX_2 50
#define GPIOX_3 51
#define GPIOX_4 52
#define GPIOX_5 53
#define GPIOX_6 54
#define GPIOX_7 55
#define GPIOX_8 56
#define GPIOX_9 57
#define GPIOX_10 58
#define GPIOX_11 59
#define GPIOX_12 60
#define GPIOX_13 61
#define GPIOX_14 62
#define GPIOX_15 63
#define GPIOX_16 64
#define GPIOX_17 65
#define GPIOX_18 66
#define GPIOX_19 67
#define GPIOZ_0 68
#define GPIOZ_1 69
#define GPIOZ_2 70
#define GPIOZ_3 71
#define GPIOZ_4 72
#define GPIOZ_5 73
#define GPIOZ_6 74
#define GPIOZ_7 75
#define GPIOZ_8 76
#define GPIOZ_9 77
#define GPIOZ_10 78
#define GPIOZ_11 79
#define GPIOZ_12 80
#define GPIO_TEST_N 81
#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */

2
include/dt-bindings/interrupt-controller/apple-aic.h
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@ -11,5 +11,7 @@
#define AIC_TMR_HV_VIRT 1
#define AIC_TMR_GUEST_PHYS 2
#define AIC_TMR_GUEST_VIRT 3
#define AIC_CPU_PMU_E 4
#define AIC_CPU_PMU_P 5
#endif

75
include/dt-bindings/memory/tegra234-mc.h
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@ -1,4 +1,5 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
@ -7,15 +8,59 @@
#define TEGRA234_SID_INVALID 0x00
#define TEGRA234_SID_PASSTHROUGH 0x7f
/* NISO0 stream IDs */
#define TEGRA234_SID_APE 0x02
#define TEGRA234_SID_HDA 0x03
#define TEGRA234_SID_PCIE0 0x12
#define TEGRA234_SID_PCIE4 0x13
#define TEGRA234_SID_PCIE5 0x14
#define TEGRA234_SID_PCIE6 0x15
#define TEGRA234_SID_PCIE9 0x1f
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
#define TEGRA234_SID_PCIE1 0x05
#define TEGRA234_SID_PCIE2 0x06
#define TEGRA234_SID_PCIE3 0x07
#define TEGRA234_SID_PCIE7 0x08
#define TEGRA234_SID_PCIE8 0x09
#define TEGRA234_SID_PCIE10 0x0b
#define TEGRA234_SID_BPMP 0x10
/*
* memory client IDs
*/
/* High-definition audio (HDA) read clients */
#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
/* PCIE6 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
/* PCIE6 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
/* PCIE7 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
/* PCIE7 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
/* PCIE8 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
/* High-definition audio (HDA) write clients */
#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
/* PCIE8 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
/* PCIE9 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
/* PCIE6r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
/* PCIE9 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
/* PCIE10 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
/* PCIE10 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
/* PCIE10r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
/* PCIE7r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
/* sdmmcd memory write client */
@ -28,5 +73,35 @@
#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
/* BPMPDMA write client */
#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
/* APEDMA read client */
#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
/* APEDMA write client */
#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
/* PCIE0 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
/* PCIE0 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
/* PCIE1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
/* PCIE1 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
/* PCIE2 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
/* PCIE2 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
/* PCIE3 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
/* PCIE3 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
/* PCIE4 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
/* PCIE4 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
/* PCIE5 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
/* PCIE5 write clients */
#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
/* PCIE5r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
#endif

3
include/dt-bindings/pinctrl/k3.h
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@ -41,4 +41,7 @@
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#endif

1174
include/dt-bindings/pinctrl/mt8186-pinfunc.h Normal file
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179
include/dt-bindings/pinctrl/sppctl-sp7021.h Normal file
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@ -0,0 +1,179 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Sunplus SP7021 dt-bindings Pinctrl header file
* Copyright (C) Sunplus Tech/Tibbo Tech.
* Author: Dvorkin Dmitry <dvorkin@tibbo.com>
*/
#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
#include <dt-bindings/pinctrl/sppctl.h>
/*
* Please don't change the order of the following defines.
* They are based on order of 'hardware' control register
* defined in MOON2 ~ MOON3 registers.
*/
#define MUXF_GPIO 0
#define MUXF_IOP 1
#define MUXF_L2SW_CLK_OUT 2
#define MUXF_L2SW_MAC_SMI_MDC 3
#define MUXF_L2SW_LED_FLASH0 4
#define MUXF_L2SW_LED_FLASH1 5
#define MUXF_L2SW_LED_ON0 6
#define MUXF_L2SW_LED_ON1 7
#define MUXF_L2SW_MAC_SMI_MDIO 8
#define MUXF_L2SW_P0_MAC_RMII_TXEN 9
#define MUXF_L2SW_P0_MAC_RMII_TXD0 10
#define MUXF_L2SW_P0_MAC_RMII_TXD1 11
#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12
#define MUXF_L2SW_P0_MAC_RMII_RXD0 13
#define MUXF_L2SW_P0_MAC_RMII_RXD1 14
#define MUXF_L2SW_P0_MAC_RMII_RXER 15
#define MUXF_L2SW_P1_MAC_RMII_TXEN 16
#define MUXF_L2SW_P1_MAC_RMII_TXD0 17
#define MUXF_L2SW_P1_MAC_RMII_TXD1 18
#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19
#define MUXF_L2SW_P1_MAC_RMII_RXD0 20
#define MUXF_L2SW_P1_MAC_RMII_RXD1 21
#define MUXF_L2SW_P1_MAC_RMII_RXER 22
#define MUXF_DAISY_MODE 23
#define MUXF_SDIO_CLK 24
#define MUXF_SDIO_CMD 25
#define MUXF_SDIO_D0 26
#define MUXF_SDIO_D1 27
#define MUXF_SDIO_D2 28
#define MUXF_SDIO_D3 29
#define MUXF_PWM0 30
#define MUXF_PWM1 31
#define MUXF_PWM2 32
#define MUXF_PWM3 33
#define MUXF_PWM4 34
#define MUXF_PWM5 35
#define MUXF_PWM6 36
#define MUXF_PWM7 37
#define MUXF_ICM0_D 38
#define MUXF_ICM1_D 39
#define MUXF_ICM2_D 40
#define MUXF_ICM3_D 41
#define MUXF_ICM0_CLK 42
#define MUXF_ICM1_CLK 43
#define MUXF_ICM2_CLK 44
#define MUXF_ICM3_CLK 45
#define MUXF_SPIM0_INT 46
#define MUXF_SPIM0_CLK 47
#define MUXF_SPIM0_EN 48
#define MUXF_SPIM0_DO 49
#define MUXF_SPIM0_DI 50
#define MUXF_SPIM1_INT 51
#define MUXF_SPIM1_CLK 52
#define MUXF_SPIM1_EN 53
#define MUXF_SPIM1_DO 54
#define MUXF_SPIM1_DI 55
#define MUXF_SPIM2_INT 56
#define MUXF_SPIM2_CLK 57
#define MUXF_SPIM2_EN 58
#define MUXF_SPIM2_DO 59
#define MUXF_SPIM2_DI 60
#define MUXF_SPIM3_INT 61
#define MUXF_SPIM3_CLK 62
#define MUXF_SPIM3_EN 63
#define MUXF_SPIM3_DO 64
#define MUXF_SPIM3_DI 65
#define MUXF_SPI0S_INT 66
#define MUXF_SPI0S_CLK 67
#define MUXF_SPI0S_EN 68
#define MUXF_SPI0S_DO 69
#define MUXF_SPI0S_DI 70
#define MUXF_SPI1S_INT 71
#define MUXF_SPI1S_CLK 72
#define MUXF_SPI1S_EN 73
#define MUXF_SPI1S_DO 74
#define MUXF_SPI1S_DI 75
#define MUXF_SPI2S_INT 76
#define MUXF_SPI2S_CLK 77
#define MUXF_SPI2S_EN 78
#define MUXF_SPI2S_DO 79
#define MUXF_SPI2S_DI 80
#define MUXF_SPI3S_INT 81
#define MUXF_SPI3S_CLK 82
#define MUXF_SPI3S_EN 83
#define MUXF_SPI3S_DO 84
#define MUXF_SPI3S_DI 85
#define MUXF_I2CM0_CLK 86
#define MUXF_I2CM0_DAT 87
#define MUXF_I2CM1_CLK 88
#define MUXF_I2CM1_DAT 89
#define MUXF_I2CM2_CLK 90
#define MUXF_I2CM2_DAT 91
#define MUXF_I2CM3_CLK 92
#define MUXF_I2CM3_DAT 93
#define MUXF_UA1_TX 94
#define MUXF_UA1_RX 95
#define MUXF_UA1_CTS 96
#define MUXF_UA1_RTS 97
#define MUXF_UA2_TX 98
#define MUXF_UA2_RX 99
#define MUXF_UA2_CTS 100
#define MUXF_UA2_RTS 101
#define MUXF_UA3_TX 102
#define MUXF_UA3_RX 103
#define MUXF_UA3_CTS 104
#define MUXF_UA3_RTS 105
#define MUXF_UA4_TX 106
#define MUXF_UA4_RX 107
#define MUXF_UA4_CTS 108
#define MUXF_UA4_RTS 109
#define MUXF_TIMER0_INT 110
#define MUXF_TIMER1_INT 111
#define MUXF_TIMER2_INT 112
#define MUXF_TIMER3_INT 113
#define MUXF_GPIO_INT0 114
#define MUXF_GPIO_INT1 115
#define MUXF_GPIO_INT2 116
#define MUXF_GPIO_INT3 117
#define MUXF_GPIO_INT4 118
#define MUXF_GPIO_INT5 119
#define MUXF_GPIO_INT6 120
#define MUXF_GPIO_INT7 121
/*
* Please don't change the order of the following defines.
* They are based on order of items in array 'sppctl_list_funcs'
* in Sunplus pinctrl driver.
*/
#define GROP_SPI_FLASH 122
#define GROP_SPI_FLASH_4BIT 123
#define GROP_SPI_NAND 124
#define GROP_CARD0_EMMC 125
#define GROP_SD_CARD 126
#define GROP_UA0 127
#define GROP_ACHIP_DEBUG 128
#define GROP_ACHIP_UA2AXI 129
#define GROP_FPGA_IFX 130
#define GROP_HDMI_TX 131
#define GROP_AUD_EXT_ADC_IFX0 132
#define GROP_AUD_EXT_DAC_IFX0 133
#define GROP_SPDIF_RX 134
#define GROP_SPDIF_TX 135
#define GROP_TDMTX_IFX0 136
#define GROP_TDMRX_IFX0 137
#define GROP_PDMRX_IFX0 138
#define GROP_PCM_IEC_TX 139
#define GROP_LCDIF 140
#define GROP_DVD_DSP_DEBUG 141
#define GROP_I2C_DEBUG 142
#define GROP_I2C_SLAVE 143
#define GROP_WAKEUP 144
#define GROP_UART2AXI 145
#define GROP_USB0_I2C 146
#define GROP_USB1_I2C 147
#define GROP_USB0_OTG 148
#define GROP_USB1_OTG 149
#define GROP_UPHY0_DEBUG 150
#define GROP_UPHY1_DEBUG 151
#define GROP_UPHY0_EXT 152
#define GROP_PROBE_PORT 153
#endif

31
include/dt-bindings/pinctrl/sppctl.h Normal file
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@ -0,0 +1,31 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Sunplus dt-bindings Pinctrl header file
* Copyright (C) Sunplus Tech / Tibbo Tech.
* Author: Dvorkin Dmitry <dvorkin@tibbo.com>
*/
#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__
#define __DT_BINDINGS_PINCTRL_SPPCTL_H__
#define IOP_G_MASTE (0x01 << 0)
#define IOP_G_FIRST (0x01 << 1)
#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE)
#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE)
#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00)
#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */
#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */
#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */
#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */
#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */
/*
* pack into 32-bit value:
* pin# (8bit), typ (8bit), function (8bit), flag (8bit)
*/
#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \
((fun) << 8) | (flg))
#endif

35
include/dt-bindings/power/imx8mp-power.h Normal file
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@ -0,0 +1,35 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
*/
#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0
#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1
#define IMX8MP_POWER_DOMAIN_USB1_PHY 2
#define IMX8MP_POWER_DOMAIN_USB2_PHY 3
#define IMX8MP_POWER_DOMAIN_MLMIX 4
#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5
#define IMX8MP_POWER_DOMAIN_GPU2D 6
#define IMX8MP_POWER_DOMAIN_GPUMIX 7
#define IMX8MP_POWER_DOMAIN_VPUMIX 8
#define IMX8MP_POWER_DOMAIN_GPU3D 9
#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10
#define IMX8MP_POWER_DOMAIN_VPU_G1 11
#define IMX8MP_POWER_DOMAIN_VPU_G2 12
#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13
#define IMX8MP_POWER_DOMAIN_HDMIMIX 14
#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15
#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16
#define IMX8MP_POWER_DOMAIN_HSIOMIX 17
#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18
#define IMX8MP_HSIOBLK_PD_USB 0
#define IMX8MP_HSIOBLK_PD_USB_PHY1 1
#define IMX8MP_HSIOBLK_PD_USB_PHY2 2
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
#endif

3
include/dt-bindings/power/imx8mq-power.h
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@ -18,4 +18,7 @@
#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
#define IMX8M_POWER_DOMAIN_PCIE2 10
#define IMX8MQ_VPUBLK_PD_G1 0
#define IMX8MQ_VPUBLK_PD_G2 1
#endif

19
include/dt-bindings/power/meson-s4-power.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2021 Amlogic, Inc.
* Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_S4_POWER_H
#define _DT_BINDINGS_MESON_S4_POWER_H
#define PWRC_S4_DOS_HEVC_ID 0
#define PWRC_S4_DOS_VDEC_ID 1
#define PWRC_S4_VPU_HDMI_ID 2
#define PWRC_S4_USB_COMB_ID 3
#define PWRC_S4_GE2D_ID 4
#define PWRC_S4_ETH_ID 5
#define PWRC_S4_DEMOD_ID 6
#define PWRC_S4_AUDIO_ID 7
#endif

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