linux-xiaomi-chiron/arch/csky/include/asm/cacheflush.h

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_CSKY_CACHEFLUSH_H
#define __ASM_CSKY_CACHEFLUSH_H

#include <linux/mm.h>
#include <abi/cacheflush.h>

#endif /* __ASM_CSKY_CACHEFLUSH_H */
csky: Cache and TLB routines This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2018-09-05 14:25:10 +08:00			`/* SPDX-License-Identifier: GPL-2.0 */`

			`#ifndef __ASM_CSKY_CACHEFLUSH_H`
			`#define __ASM_CSKY_CACHEFLUSH_H`

csky: Add flush_icache_mm to defer flush icache all Some CPUs don't support icache.va instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> 2020-01-31 20:33:10 +08:00			`#include <linux/mm.h>`
csky: Cache and TLB routines This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2018-09-05 14:25:10 +08:00			`#include <abi/cacheflush.h>`

			`#endif /* __ASM_CSKY_CACHEFLUSH_H */`